Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Yesterday DAC hosted the first ever Virtual Platform Workshop, a full day dedicated to the topic. Everybody I talked to at the event was very happy to see a full day devoted to the topic. There was a lot to learn from each other. Grant Martin has already posted some comments on the event.
I participated in the lunch panel which served as the mealtime entertainment. The other panelists were:
I'll try to summarize the main points of each speaker. I'm probably missing some things from memory, but feel free to post clarifications as comments.
Jose: Virtual Platforms are key to shortening time to revenue for new devices. Software comes at the end of the process and schedule delays can result in $10 M per week of lost revenue. Shifting the schedule for parallel development improves time to revenue.
John: Helping customers get chips done sooner is important for ARM. Complexity is growing rapidly, and providing models for ARM IP for Virtual Platform usage is important.
Simon: Multicore debugging is the straw that will break the camel's back and force software engineers to do more work using Virtual Platforms so they can gain visibility and control to deliver multicore software. Providing familiar interfaces for software engineers, such as gdb and eclipse, are important.
Jason: Bugs in hardware dependent software are critical and we need to use better verification tools to stress the hardware-software boundary, not just manual testing. More automation to utilize the Virtual Platform for constrained random verification is important. High-level synthesis will connect the design process to the Virtual Platform.
Mark: SystemC is not the best technically, but has been very good as a standard to bring the community together, so continue to focus on standards and use SystemC. Models should be free from the IP vendor. Sometimes, host-code execution and virtualization can be used in the context of Virtual Platforms.
In the question and answer part we discussed some past challenges with Virtual Platforms and why it is sometimes difficult for software engineers to adopt them. Some challenges include:
The panel ended with a chance to predict what will be different at DAC 2010 in the area of Virtual Platforms. Although nobody had any earth shattering predictions, Mark Johnstone from Freescale went out on a limb and said that High Level Synthesis will be so successful that the software engineers will be writing SystemC and become hardware engineers, and that hardware engineers will use the skills they have in understanding parallelism to be able to write software for multicore systems.
Thanks to everybody that attended.
Thanks, Jason, for your article. I found Mark's comments to be very interesting ... and note that he describes what software engineers could do on one hand, hardware engineers on the other. But what about both of them, together? That points out a need for change in both process and organization.
I'm a former customer of Mentor's Seamless CVE and have used it for creating virtual prototypes. That product has been around for a while, so people have been using it for a while ... if they have the right user profile. It will be interesting to see if necessity will drive more users into such a profile (hw and sw team members working together, or coordinated by a program manager).
Disclaimers: as noted, I was a customer of Seamless CVE. And then I was on that program during my initial period at Mentor Graphics, where I worked until recently. But now, I'm of an open mind! (: