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Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in Germany, to the TeamESL blog for the next installment on post-silicon embedded software verification with ISX.
This post is a discussion featuring Markus and Joerg talking to Malte Henzelmann and Ernst Zwingenberger of El Camino GmbH. It builds on the introduction that was provided in June titled OVM Metric Driven Verification with an FPGA-based Design.
In various projects where we were using ISX for HW/SW co-verification it turned out that the coverage driven verification approach is very powerful for SW verification as well. Due to our expertise in both worlds, FPGA and Coverage Driven Verification, we already liked the idea of bringing both worlds together. Finally, a customer request was the impetus to do it.
This project sounds like a lot of fun. Tell us something about yourselves and your background.
Malte was working as scientific assistant from 2001 to 2006 doing research in the area of formal verification, particularly abstraction techniques. Since 2007 he has been a verification engineer at El Camino doing verification of a display controller and a PCIe to AXI bridge with Specman and Incisive Formal Verifier. He also worked on the test utilization of ISX in combination with a FPGA board.
Ernst is currently head of verification at El Camino. From 2004 to 2006 Ernst was System-On-Chip Verification Engineer responsible for Coverage Driven Verification Methodology and Verification Concepts at Micronas GmbH in Munich. Prior to that, he was a Verification Consulting Engineer at El Camino focused on Coverage Driven Verification and design of reusable Verification Components.
You have been working for El Camino as Cadence Verification Alliance Partner for many years. What are the main areas you are working on?
The main areas of focus for El Camino are engineering and verification services around FPGA, ASIC, and Embedded Systems/Software as well as board layout.
Tell us more details about the Altera board (CPU types, max. design size)
One of the really cool characteristics of this interface is the fact that it uses the standard JTAG port together with the standard Altera download hardware. This means that virtually every Altera based FPGA board can be used. Also in terms of CPU types there’s no real limitation. All that needs to be done is to instantiate a special on-chip dual-port memory function from El Camino. One port is automatically connected to the JTAG interface of the FPGA while the other port has to be connected to the CPU. This can be setup on off-the-shelf FPGA boards but also on application specific platforms. The biggest FPGA that’s currently available from Altera is the EP4SGX530, which has 530,000 Logic Elements, plenty of room for complex, embedded systems.
What tools did you use in your verification flow?
Cadence Incisive Enterprise Specman Elite Testbench with the Enterprise System-Level (ESL) Option
What about visibility of the hardware and debug options?
Internal hardware nodes are visible through Altera’s SignalTap embedded Logic Analyzer. Furthermore there’s SignalProbe which allows us to route individual nodes to test pins or the Logic Analyzer Interface, which allows the multiplexing of internal groups of signals to a set of test pins.
The software debugging options depend on the CPU used. For example, there’s the μVision Debugger for the ARM Cortex-M1 or the GNU based NIOS II IDE debugger or for the NIOS II CPU. Such debuggers can simultaneously use the very same JTAG Interface and download hardware as ISX in order to control the CPU.
What group of users are you targeting for ISX on the Altera FPGA Board?
We’re targeting engineers verifying a System-on-Chip design or some IP modules integrated as a HW/SW package. Also, embedded software developers could use ISX on an FPGA board to apply coverage driven verification to their software.
What is the ideal use model for your post silicon verification solution?
Nowadays SoCs or IP modules always require a significant amount of software drivers or protocol stacks. We believe that high quality SoC and IP module (HW+SW) packages are perfect candidates.
Are you able to reuse the pre-silicon testbench?
Yes, the software e Verification Component (eVC) can be used throughout the whole verification flow. Starting with Virtual Platforms, RTL simulation/acceleration and finally on the FPGA board. With ISX you can run your software encapsulated in an eVC on all of these representations of the hardware.
Thank you for your time and thank you to all the readers out there on cadence.com.
Here is a video showing the demo board and the running ISX testbench: