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In a recent blog on EDA Graffiti, Paul McClellan he talks about Software Signoff. He loosely defines it as high level synthesis of C/C++ describing the system, with some of the code built into an FPGA and the rest remains application software. He identifies the two enabling technologies as 1) high level synthesis and the 2) FPGA. Those are necessary but not sufficient for Software Signoff. What's missing is functional verification. There's a big assumption made, that the software and FPGA will work. In today’s typical design flow hardware signoff has advanced verification whereas software is barely getting started in the domain of verification.
The notion of signoff was innovated with the emergence of ASIC foundaries, companies that provided fabrication services for companies that only wanted to specialize in silicon design. This eco system drove the emergence of companies like LSI Logic and IBM Microelectronics as leaders of large gate count, small geometry, large pin count manufacturing processes. The process of Signoff was handing a manufacturing "tape" and adjunct instructions. This milestone was called "tape out", and literally was based on delivering a GDS-II format file on a tape reel. It was called Signoff because the design company signed that if the ASIC foundary built what was described on the tape, they would be paid. The design company retained responsibility of the quality of the design.
We fast forward to today's world where ASIC foundaries have consolidated but the esssence of tapeout has shifted to different formats, primarly RTL handoff. The modern EDA industry emerged to enable the move from GDS-II handoff to RTL handoff. On the design side this has meant innovations in static timing analysis, physical-aware synthesis, formal verification, and more. What has remained constant is the need for the design company to be responsible for the quality of the design. Thus the emergence of verification as a dominant challenge for today's SoC development.
But wait, software is also dominant, and thus the idea of Software Signoff is very appealling. However, we first need to help our customers with Software Verification. The application view that Paul is talking about is important. Virtual or FPGA prototypes are useful for running software. But does that mean it's been verified? It's been proven repeatedly in the silicon domain that no, there must be a rigorous approach to verification, and this applies to Software as well. Or you risk not knowing if what you're building will work.
Cadence is innovating the application of hardware advanced verification concepts and solutions to the domain of software. First with co-verifciation and co-debug, FPGA based software verification, and subsequently middle ware and applications. You'll find blogs here about each. In the past and in the future... Stay tuned for more!