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2010 was a very dynamic year for the electronic systems industry overall and Cadence in particular. In this set of blogs, I discuss some of the trends that started in 2010 and will continue in 2011. In part I, I talked about the key growth market, key industry challenges and the role of EDA. In this blog post (part II), I will talk about Cadence offerings addressing these challenges.
Cadence System Design and Verification -- Addressing IP Productivity and System Integration
In order to be successful, the System/SoC companies need to improve two key parameters in their system development:
1. Development (creation and reuse) productivity of differentiating core IP
2. SoC/System and IP integration (including HW/SW and multi-IP verification/validation)
At Cadence, we look at system-level design beyond the narrower focus of ESL. We are focusing on the customer's challenges to realize a new system. Although it is important to drive the flow from the application/software level and the specifications definition phase, ESL is one piece of the solution and not the whole solution.
We believe that the problem needs to get addressed by multiple components of the flow, must be connected to the mainstream (core EDA) flow, and needs to be developed based on a set of open, standards-based solutions. We believe the solution needs to be scalable and should rely on an expansion of existing products and methodologies available in the market. To address the key challenges mentioned above, Cadence's short-term systems strategy focuses on two vectors:
1. Move design and verification to a higher-level of abstraction to enhance productivity and predictability. In 2010, we introduced the industry's first TLM-driven Design and Verification methodology book with a focus on IP design and verification to articulate our recommended methodology. It includes a top-down design flow with examples based on the C-to-Silicon Compiler high-level synthesis (HLS) tool, which works with an embedded Encounter RTL Compiler and the Calypto SLEC System-HLS equivalence checker. It also provides an optimized path to Altera and Xilinx FPGAs and to Cadence Palladium Series/Palladium XP emulators.
Other unique features build into this methodology include Engineering Change Order (ECO) capabilities that combine C-to-Silicon and Encounter Conformal ECO together with a top down metric-driven verification flow based on the Incisive Enterprise Simulator and the OVM/UVM methodologies. Feedback about the flow and the methodology has been provided by industry experts Grant Martin and Brian Bailey, and companies such as Casio, ST, TI and Fujitsu. In 2011, we are planning to proliferate and enhance the above flows with a focus on ease-of-use to provide faster time-to-RTL, enhance quality of results (QoR) and improve the TLM-to-GDS flow. We are also going to extend these flows beyond a single IP block. One of our key challenges is to educate the industry (and the individual teams) about C++/SystemC to make them comfortable with the new flows. The good news is that we are starting to see large companies building the infrastructure to support these flows.
2. Provide an integrated HW/SW development solution to improve quality and time-to-market. As I have stated above, System/SoC (HW/SW), IP integration and bring-up time are becoming the bottlenecks in any new complex digital design, especially in the consumer market. Pre-silicon HW/SW development platforms are becoming an essential part of the system integration and validation phase. They enable performance and capacity scalability and provide a vehicle to verify and debug your hardware and software.
In 2010, we have seen significant increase in the demand for System/SoC integration, verification and validation. RTL testbench simulation alone can't address the full system verification problem as a result of increased HW design complexity and the popularity of embedded processor/cores. HW-assisted verification plays a major role here and is currently the largest commercial revenue component that can address these challenges. In 2010 Cadence introduced the Palladium XP Verification Computing Platform, which combines simulation, acceleration and emulation into a single platform. It provides, for the first time, impressive emulation performance that can reach 4 MHz while maintaining the strengths of Palladium emulation and Xtreme acceleration. Palladium XP received feedback from customers such as nVidia and Nethra Imaging. Starting in 2010 and continuing in 2011, we are expending the traditional emulation and transaction-based acceleration use models adding Metric-Driven Verification and low-power verification and analysis. Some examples for these flows can be provided through presentations from ARM, Freescale, TI and Broadcom.
3. With the need to rely on outsourcing and external IP and the pressure to integrate multiple IPs quickly into an SoC, Verification IP is becoming a "must have". Cadence continues to expand its portfolio with 3 dimensions:
a. Expansion of the core testbench simulation Verification IP leveraging Denali IP and our internal VIP.
b. Expansion of Verification IP to support multiple levels of abstraction and multiple platforms.
c. Expansion of our rich SpeedBridge portfolio and "real world" interfaces.
4. As we have discussed above, we at Cadence can't do it alone and therefore need to partner with others in order to deliver a complete flow. In this section, I will focus on the ecosystem. In 2010, Cadence announced its System Realization collaboration with Wind River and ARM and its contribution to the TSMC ESL reference flow 11. Later on, we have introduced the System Realization Alliance with 20+ partners. These partners including IP, Software, EDA and service providers (including education and training) companies. In the last few months, we have delivered together with these partners multiple webinars to educate the market with the new technologies and the mutual flows with Cadence. These companies include Xtreme EDA, CircuitSutra, Imperas, Calypto, ARM, TSMC, CoFluent, Jeda Technologies and Magillem. You should expect to see more collaboration in 2011between Cadence and the System Realization Alliance members.
Finally, Cadence continues to be very active in driving some of the key system standardization activities including Open System Initiative (OSCI) with its focus on TLM-2.0, SystemC synthesizable subset, and overall interoperability;SystemC IEEE 1666; Accellera with its focus on the Interface Technical Committee (developing standard co-emulation API -- SCE-MI which is migrating now to 2.1); Unified Coverage Interoperability (UCIS); IP-XACT; Verification IP interoperability and UVM.
I wish all of you a happy new year. As always, I am interested to hear your feedback.