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As part of this week's System Development Suite announcement, Cadence introduced two new platforms, the Virtual System Platform and the Rapid Prototyping Platform. Both new platforms help users start embedded software development much earlier, thus providing an accelerated path to revenue.
I'm particularly excited about the Rapid Protoyping Platform (shown below) for multiple reasons. For one it is a natural extension and complement to our successful Verification Computing Platform, also known as Palladium XP. But mostly I'm excited because it was about time that somebody is trying to do FPGA-based prototyping right and is solving the major user complaints and issues -- prototype bring-up time, functional correctness and debug!
Today, prototyping bring-up time for a multi-FPGA prototype can take several months until everything is up and running with the desired functionality. This is mostly caused by an FPGA-specific implementation flow that forces the user to modify the design RTL, remodel memories, have FPGA expertise, and so on. Some vendors even go so far as to publish a book about the FPGA prototyping methodology, trying to convince you that you must design your ASIC with FPGA-based prototyping in mind -- really?
The next issue is how to validate that your FPGA implementation is still functionally correct after all the FPGA-specific transformations, and is representing the original design. Today that is mostly done on the running FPGA-based prototype, and it ususally requires many time-consuming iterations. And yet, you still always have the uncertainty if a suspicious behavior is a design bug, an issue with the FPGA-specific transformation, or even a faulty FPGA board.
And finally the debugging capabilities in today's FPGA-based prototypes are pretty limited and cumbersome to use.
The new Rapid Prototyping Platform is addressing and solving all the above issues in a unique and highly productive way. It uses an ASIC design flow with extremely fast compile times and does not require design changes, memory remodeling or any other FPGA-specific modifications. It even allows the reuse of most of the Palladium environment like memory definitions, clock definitions, and scripts.
Validation of the correctness is done prior to the time-consuming FPGA place and route step by automatically generating a post-partitioning model that already includes all FPGA-specific transformations. This model is ideally run on the Verification Computing Platform against the golden test environment.
For design debug the user has multiple options. One option is using the more traditional approach of probing selected, pre-defined signals during runtime, but a more powerful approach is to re-run failed tests on the Verification Computing Platform and using all its advanced debug capabilities.
The new Rapid Prototyping Platform is taking a new approach to FPGA-based prototyping, addressing the user's real problems and making it, for the first time, a easy to use and highly productive methodology.
I would love to hear from you, the users, what your experience with FPGA-based prototyping is. What are your challenges, and what is your on your wish list?