Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
I've been at CDNLive! EMEA watching demos of the newly announced System Development suite, and it's mindblowing. I'm seeing good old ncsim running Android interactively on the Virtual System Platform. You open an app in the virtual Android interface and you can stop the software, or even the hardware model, at a breakpoint in ncsim. I'm seeing FPGA prototypes compiled at light speed with the Rapid Prototyping Platform. From a big picture perspective, Richard Goering's "The Story is the Continuum" really sums up the biggest deal here.
The language used to describe the early virtual prototype is SystemC TLM. Yes, I've been blogging about high-level synthesis in C-to-Silicon Compiler using SystemC TLM. Now we have a clear bridge between hardware and software. Keep in mind that even within TLM you can have different levels of detail. What you describe for the virtual prototype is essentially the algorithm, untimed, at a high level, so it can simulate really fast. You would refine that description for high-level synthesis, adding hardware architecture detail such as partitioning into threads and adding approximate timing for the system bus interfaces.
The hardware designers can start doing this with the same code that the architects use to create and verify the algorithm. It's just a refinement step. And there is still work for the hardware design team -- they have to specify the high-level constraints for synthesis and drive it toward an RTL implementation that will meet the spec of the target application. So this is a refinement process that is now connected all the way from early algorithm development and verification down into traditional implementation.
And verification is also connected. The virtual prototype becomes the golden reference model that simulation checks against when you're verifying each step of this refinement process. The really nice part is that each step can re-use the same verification environment and report back metrics.
Once enough verification has been run and implementation is underway, the RTL generated from C-to-Silicon high-level synthesis can be loaded onto the Rapid Prototyping Platform for even faster software development and verification. The entire process is connected! And if an issue is identified at this late point in the design cycle? You can fix the synthesizable TLM and C-to-Silicon can run in ECO mode, passing forward patch information to Conformal ECO, which can apply a patch at any point of implementation. Connected!
So this is an exciting announcement for many reasons -- and we are only just getting started.