Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
John Blyler, Editorial Director at Extension Media, presented in our EDA360 Theatre at DAC 2012 about "ASIC/ASSP Prototyping with FGPAs" and provided an update on his annual survey on this topic. The current 2012 survey is actually currently ongoing and you can still participate here.
FPGA-based prototyping is the fourth pillar in the Cadence System Development Suite. The unique advantage of the Cadence solution, called Rapid Prototyping Platform (RPP), is its proximity to the Palladium XP Verification Computing Platform (VCP) and the application of the same ASIC front-end flow (as opposed to FPGA centric flows in roll-your-own or other commercial offerings). The big issue in FPGA based prototyping is the bring-up time, which is often dominated by making sure before actual bring-up that after all modifications to an RTL stop, one actually still has the same functionality that was put into the flow. In the Cadence flow the netlist targeted to the RPP can be used on Palladium without modification, allowing more efficient verification. Together with applying an ASIC optimized flow, automated partitioning and the re-validation on Palladium, the typical bring-up time of four to six months for roll-your-own solutions and other commercial offerings can be reduced to weeks.
So what does FPGA prototyping enable? In the System Development Suite vision, the focus of FPGA based prototyping is software development and running verification regressions. While its speed is in the range of 10s of MHz, faster than emulation which is in the MHz range, its debug observability into the hardware is much more limited. Software debug feels similar to debug on the development board with the actual chip, because it is using standard JTAG connections and standard software debug environments. Because it is available well before silicon, it definitely beats having to wait for the actual chip to be plugged into the development kit when it becomes available. Finally, due to its speed, letting FPGA based prototypes run in the actual live environment of the chip under development and connect to real world interfaces like Bluetooth, Ethernet, USB etc. becomes a whole lot easier.
That's our story ... so how does it compare to actual user priorities? Quite ,actually, according to surveys! John Blyler ran a survey for a couple of years now. Survey questions focused on demographics, end-user application markets, design specifications, tool usage, verification types, methodologies and prototyping techniques. In John's 2010 survey, conducted in October 2010, a total of 110 filtered designers (taking out Universities etc.) participated in this survey. When asked "If you are using or are planning to use FPGA based prototyping, please describe the use mode," the responses looked as follows:
The largest number of respondents referred to "HW/SW Co-Design and Co-Verification" as their main use model, loosely followed by HW/Chip verification. If we add in "System Validation" and "System Integration" - both involving the software and the hardware - and the actual "Software Development," then the use models closely involving software definitely have a leg up.
The other use model that's interesting here is the 30% of respondents identifying "IP Development and Verification." Given the complexity of the chips which we are talking about prototyping here, verifying the IP or the sub-systems to be integrated into those chips definitely is an attractive use model. Note that software may play a role here, especially when it comes to sub-system verification involving processors.
The last use model - Post Silicon Debug - is interesting in itself as well. All prototyping techniques - virtual, emulation and FPGA-based -- have their place even after silicon is available. The better controllability compared to the actual chips are probably the central driver here.
Bottom line, it looks like the results of this survey confirm the vision of the System Development Suite we have been working towards. Software related use models and verification are the main drivers. It will be interesting to see whether the trend continues, so please help John Blyler and us by providing input to the most recent 2012 survey here!
I will make sure to update you on the results when I have them.