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From an electronics point of view, "the internet of things" (I'll stick with that name) may come across as something that will drive processor cores and microcontrollers, along with all kinds of sensors. But where is the opportunity for high-level synthesis?
Sensors of course are in the analog world because they interact with the real world. Processor cores and microcontrollers are concentrated amongst a handful of vendors, and are high-volume. These vendors can afford armies of engineers writing RTL to squeeze out every last bit of area, right? Kind of like Intel in the PC microprocessor era, designing at the transistor level? Yes and no.
We already have customers who use high-level synthesis (HLS) for microcontrollers. It speeds their time-to-market, but more importantly it allows them to adapt for different requirements. If your chip is going into Rover's dog tag, it will have different power requirements than if it's going into your refrigerator. It is much easier to change HLS constraints or specify a different microarchitecture during the HLS process than it is to go in and manually change the micro-architecture of your RTL. A lot less verification will be required for sure.
But even if you're a systems company that is going to purchase a microcontroller or processor core, along with the requisite sensors, it's likely that you will want your own special sauce to differentiate your product. For instance, maybe you want to sell security cameras that automatically recognize friendly faces. Facial recognition is a data-intensive algorithm, and in a security application you would want very low latency, so it would need to be implemented as hardware.
It's likely that you don't have an army of engineers on staff to write and verify tens or hundreds of thousands of lines of RTL (and more lines of human-written code introduces more chances for bugs, which you want to avoid in the security business!). And it's likely that you already have a C/C++ model of your algorithm that you used for system testing. This is a typical scenario we have seen in our customers. With a couple of hardware engineers -- and yes, this requires hardware engineering expertise, good hardware still cannot be built with magic -- they can adapt the C/C++ model using SystemC so that it will efficiently synthesize to hardware that meets your business requirements.
The resulting model can eventually be adapted to suit both needs -- high-speed system prototyping and efficient hardware implementation -- in a single source using the guidelines described by Stuart Swan in this video. Thus the model can be very easily re-used in future products. And with this expertise, all new models can be developed in such a manner. You don't have to do the RTL-GDSII yourself if it's not a core competency; there are plenty of design houses willing to contract that work.
This model is beginning to sound a lot like the ASIC model that really took off as part of the PC and internet growth engines. Even though processors were in everything and were being designed at the transistor level, there was a huge amount of growth in the ASICs that surrounded them as systems companies complemented these processors with their own innovative hardware. Eventually most of the functionality of the standalone ASICs was consolidated into SoCs, as happens when industries mature. But during the growth phase, most of the innovation happens in the domain experts -- the systems companies.
The internet of things presents a tremendous opportunity for growth in hardware design. All of the real world signal data coming in through all these sensors must be processed before it can be stored or consumed by the processors and microcontrollers. Many of these applications are algorithm-intense with low-latency requirements -- any sort of image, video, or audio for instance -- so hardware implementation is a must. The most economically-viable means of accomplishing this is now to utilize high-level synthesis. Many companies and engineers have already come to this realization and are widely deploying high-level synthesis. For more information on how, come visit the Cadence booth at the Design Automation Conference (DAC) in Austin June 3-5!