Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
The first day of DAC starts off today with four great
presentations on system design at our DAC Theatre. Freescale will
present on their use of FPGA-based prototyping, AMD will show their enhanced
use of Palladium together with TLM models, ARM will present their model and
debug connections to all System Development Suite (SDS) engines, and Broadcom will
round up today's SD-related presentations outlining their use of Palladium
with advanced embedded testbenches.
Freescale will kick it off at 9:30am with a presentation
titled "Implementation of a Multi-threaded 64-bit Power Architecture Core on
the RPP, FPGA-based Prototyping System". They will outline the advantages of
using Palladium Emulation in conjunction with FPGA-based prototyping. While
emulation on Palladium offers easier bring up, better hardware debug, and higher
capacity of gates, memories, etc., using RPP FPGA-based prototyping is about
10X faster and more accessible to software developers at lower cost. They will
describe the build of the e6500 PPC core on RPP. As a result, they were able to
quickly run CoreMark and many other benchmarks for performance validation and
were able to get performance metrics via the Nexus trace through the external DDR
memory interface. For benchmarking, they rebuilt design changes for performance in about a day or two, and completed and tested software/compiler optimizations for benchmarks within minutes.
That's quite a set of results, showing nicely the different
sweet spots for emulation and FPGA-based prototyping. While FPGA-based
prototyping is great for software development, our Palladium XP offers 2.5X
faster turnaround time for isolating and debugging compared to its nearest
competitor, helping to remove those bugs in the critical path of customer
AMD will talk at 12:30pm about "Complementing In-Circuit
Emulation with Virtualization for Improved Efficiency, Debug Productivity and
Performance". They consider the benefits of emulation to be growing by the day, with
users looking to emulation and other technologies to improve their productivity.
To meet the new challenges, new complementary usage models for emulation are
emerging and AMD will specifically talk about hybrid emulation with virtual
platforms and embedding devices inside emulators using accelerated VIP. With
those hybrids, AMD was able to improve application-level performance compared
to traditional emulation by factors of 2X-20X and experience improved software debug
using Virtual Platform debuggers.
At 2:00pm, ARM will present on "Accelerating Your Time to
Market with ARM Software Development Tools and the Cadence System Development
Suite". The presentation will center around how both ARM Fast Models for
processors and interconnect can be used together with the SDS engines for
actual execution, as well as how the Development Studio 5 (DS-5) connects to
Virtual Prototyping, Palladium XP, and RPP FPGA-based prototyping for software
debug. The following graph depicts the connections.
Finally, at 2:30pm, Broadcom will talk about "Faster System Bring-up with an Embedded Testbench on Palladium". They will introduce the
challenges for firmware and hardware pre-silicon co-development, including "Pre-Silicon
SoC Level Verification" with complicated and long duration firmware algorithms
and concurrent operations; "Pre-Silicon Hardware and Software Co-Debug" with functional
block configuration, fluid hardware interface (register bit-field) definitions,
peripheral devices coexistence and correct
clock ratios; "Pre-Silicon Performance Measurement", "Pre-Silicon Device Driver
Development"; and "Pre-Silicon Power Management Verification". As for their approach on Palladium, they will describe
a fully synthesizable testbench with firmware-controlled peripheral models
capable of behaving like the actual device (PID, VID, transfer size, and buffer
size) for camera, LCD, SIM, etc. Their results were nothing short of fantastic -
they experienced the fastest SoC bring-up ever, were able to provide
development platforms to software teams, and found critical system integration
This is shapig up to be quite an exciting day for system design
at DAC. It is always great to see real users show real experiences - see you at
our DAC Theatre!