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Hi,I am in the process of running a multiple chip simulation for one of our FPGA based projects using the NCLAUNCH tool. I encountered a Fatal Error after running the simulation for around 8ms, the details of which are posted below :ncsim: *internal* (System virtual memory limit exceeded (0x5000/0xbfef9198)).Observed simulation time : 8991853460 PS + 3Please contact Cadence Design Systems about this problem and provide enough information to help us reproduce it.The complete run-time of the simulation is around 100ms. Please note, i did not dump any waveforms during the simulation run. Could you kindly update me more on this error and any solutions to deal with this?Thanks,Dina
There are a number of things that can cause a Virtual Memory limit issue.Can you provide a bit more information? Are you on Linux? 64bit or 32bit?What version of NC are you using? One thing you could do to help us sort this out would be to run your design with the -profile switch and send us the prof.out file that gets produced.It may take a bit longer to run but it could give us a hint. The fact that you are running outto a certain point in sim time and then running out of memory may point to some design construct. The prof.out will tell us.Best RegardsDoug
Dina,Here are some other things you could do/check. If it applies to your particular simulation run.* Upgrade your software.Each successive NC-Verilog simulator release has shown significant improvementin memory efficiency. Thus, upgrading to the latest NC-Verilog simulator releasealways improves memory performance.* Limit access to those portions of a design being actively debugged.You can use an access control file to limit the scope of read, write, andconnectivity access in a design. See the section, “Using -afile to Include anAccess File,” in the chapter, “Elaborating with ncelab,” in the NC-VerilogSimulator Help for details on using an access control file.Similarly, you can further improve simulation speed and reduce memory usage byeliminating the need for line-based debug access to source code, for example,by eliminating line-based breakpoints. By default, the simulator does notretain this type of access. You can retain this type of access by using thencvlog -linedebug option, but this option has a significantly negative impact onsimulation performance.* Do not place probes on signals you do not need to debug.Placing probes on every signal in a design can consume more memory than thesimulation model itself. Restricting the range of probe points to those portionsof the design being actively debugged can save significant memory resources.* Run a simulation with timing checks disabled.Running a simulation without timing checks can save meaningful amounts ofmemory. The memory efficiency of these checks has been significantly improved inrecent releases of the software, but they still add overhead to the simulation. Youcan disable timing checks from the command line, or you can enable and disablethem for particular portions of the circuit using a timing control file. See thesection, “Disabling Timing in Selected Portions of a Design,” in the chapter,“Elaborating with ncelab,” in the NC-Verilog Simulator Help, for more detailedinformation on timing control files.* Avoid overusing bidirectional transistor primitives in your design.The bidirectional transistor primitives are tran, tranif0, tranif1, and theirresistive counterparts, rtran, rtranif0, and rtranif1. Overusing these primitivescan significantly increase memory usage, so they should appear only in models inwhich true bidirectional behavior is desired. A single bidirectional primitivedoes not make much difference in memory usage, but the thousands or tensof thousands that can appear in a gate-level model can add up to significantsimulation overhead. Therefore, when each pin of a bidirectional primitive hasonly a source or only a load, use a unidirectional primitive instead.
Hi Douge,Thanks for your inputs. It was really helpful. The Problem is now solved. I upgraded my exisitng nclaunch v5.5 software to a higher v5.8 version. The Internal NCSIM error vanished and the simulation ran successfully.Thanks!Cheers,Dina
Hi Dina,Glad your Internal error vanished. Have funBest RegardsDoug