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I am a beginner in verilogA .
I wrote a code but when I ran PSS it showed hidden state in the code and didn't run.
My behavioural model is as below:-
// VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga`include "constants.vams"`include "disciplines.vams"module HARD_LIMIT_GM(in,out); inout in,out; parameter real vtrans = 0; parameter real tdelay = 0 from [0:inf); parameter real trise = 1p from (0:inf); parameter real tfall = 1p from (0:inf); parameter real Gm=-5m; electrical in,out; real vout_val; analog begin @ (cross(V(in) - vtrans, 1)) vout_val = 1; @ (cross(V(in) - vtrans, -1)) vout_val = 0; I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall); end endmodule
Could anybody please tell how I can avoid the hidden state (vout_val ) ?
The reason you have a hidden state is because vout_val is not updated on every iteration. It's only set within the @cross blocks - and is held (and hence retains state) between cross events.
If you replace the two @cross statements with:
@ (cross(V(in) - vtrans)) ; vout_val = V(in)>vtrans;
Then it will do what you want. The first @cross will force there to be a timestep close to either the positive or negative transition - but doesn't have any action within the @cross itself. The second line is simply computing the vout_val based on whether V(in) is greater than vtrans - but does this at every timestep and hence is not a hidden state.
In reply to Andrew Beckett:
Thanks a lot for your reply. I have some doubts.
1:- Every iteration means:-
Is it each simulation time step ?
2:- Suppose instead of having vout_val= 1 or 0, If I want let's say vout_val= -5 ( for positive edge cross )or +7 ( for -ve edge cross ),
is there a way to achieve this ?
In reply to RFStuff:
Thanks a lot for clarifying the Hidden State problem.
Hello, I'm also new with Verilog A. I would like to run a pss in a circuit that has a block with only a veriloga view. It's a D flip-flop double edge. I wrote the veriloga code according to the advice in this post, but I still have a hidden state.
Here's the code:
// Double edge Flip Flop
module DFF_DEDGE(q, clk, d);
voltage q, clk, d;
parameter real tdelay = 1n from [0:inf),
ttransit = 20p from [0:inf),
vout_high = 1,
vout_low = 0 from (-inf:vout_high),
vth = 0.5;
@(initial_step) x = 0;
@(cross(V(clk) - vth )) x = (V(d) > vth);
V(q) <+ transition( vout_high*x + vout_low*!x, tdelay, ttransit );
If I run a PSS, I got the following error message
ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'DFF_DEDGE'. Skipped.
... : Hidden state variable: x
How can I modify the code to avoid it?
Thanks a lot!
In reply to Clidre:
See a good coverage of the problem in general in this paper on Hidden State in SpectreRF and also a hidden state free DFF model. In your case, the x variable is only updated on the crossing event, and so is clearly retaining the state of the flip flop from one iteration of the simulator to the next (which is fine normally, but not for SpectreRF as it can't see the hidden state, since it's not on a node).
The model I pointed you too uses a resetable integrator (reset on the clock edge) to achieve the same thing. This doesn't have any hidden states because the variables are updated on every timestep.
Thanks a lot!
Based on the example you pointed me, I adapted my code and this is my newest code:
// Double edge Flip Flop
module DFF_DEDGE_NOHIDDEN(q, clk, d);
parameter integer init_state=0 from [0:1];
integer actNow, out, state;
actNow = 0;
actNow = 1;
state = init_state;
@(cross(V(clk) - vth, +1) or cross(V(clk) - vth, -1)) begin
state = (V(d) > vth);
out = idt(0, state, actNow);
V(q) <+ transition(out ? vout_high : vout_low, tdelay, ttransit);
But I still have hidden state problems:
"ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'DFF_DEDGE_NOHIDDEN'. Skipped.
... Hidden state variable: state "
I've read the documentation you attached and I think that variable "state" is constantly updated. Am I missing something?
Thank you again for yuor precious help
Hello, it seems I solved it: I added state=0 and now the pss run.
This is my last working code, maybe can be useful to someone. I put in bold the line I added to make it work:
Thank you very much for your help
I am using AMS kit.
I have made circuit using schematic editor but while I am running PSS analysis, it is getting terminated with showing following error:
ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'modn_ahdl'. Skipped.
/root/cadence/ams/AMS_410_CDS/spectre/c35/soac/soac.va, declared in line 23: Hidden state variable: vgs_ot/root/cadence/ams/AMS_410_CDS/spectre/c35/soac/soac.va, declared in line 23: Hidden state variable: vds_ot/root/cadence/ams/AMS_410_CDS/spectre/c35/soac/soac.va, declared in line 23: Hidden state variable: vgb_ot/root/cadence/ams/AMS_410_CDS/spectre/c35/soac/soac.va, declared in line 23: Hidden state variable: vdb_ot/root/cadence/ams/AMS_410_CDS/spectre/c35/soac/soac.va, declared in line 23: Hidden state variable: vsb_ot/root/cadence/ams/AMS_410_CDS/spectre/c35/soac/soac.va, declared in line 23: Hidden state variable: vbpsub_ot
The same message is appearing for PSS analysis for all circuits.
Thanks and Regards,
In reply to kapiljainwal:
You will need to contact AMS. It's their model and presumably you shouldn't change it without their agreement or input. I can't advise you what to change because I've not seen the model (you can't post it here because it's AMS' IP).
I will like to know while this Normalised LMS algorithm could not be supported in PSS analysis due to the hidden state variable "WtsReg".
Can you please help proffer solution or suggestion to the code in verilogA.
// VerilogA for IM2_Cancellation, LMS, veriloga
`include "constants.vams"`include "disciplines.vams"
module LMS(clk,Inp_Sig,Error, Wts);
input clk, Error,Inp_Sig;electrical clk, Error,Inp_Sig;output Wts;electrical Wts;
parameter real mu=0.2 ; //varies between 0 to 2
integer vth; integer Clk;real ErrorReg;real WtsReg;integer Vin;real Quot;
analog begin Clk = (V(clk)> 0.5)? 1:0;
WtsReg = 0; V(Wts) <+ 0; end
if (V(Inp_Sig)) begin
ErrorReg = V(Error); V(Wts) <+ WtsReg;
@ (cross(Clk - 0.5, +1)) // rising edge of clock signal begin ErrorReg = V(Error); Quot = V(Inp_Sig)/(V(Inp_Sig)*V(Inp_Sig));
WtsReg = WtsReg + mu * ErrorReg * Quot;
In reply to Saheed Tijani:
Did you read the http://www.designers-guide.org/Analysis/hidden-state.pdf paper I pointed at earlier in this thread? The problem is that you are relying on sampling the signal at the clock edge into the variable WtsReg which is then a hidden state variable. You need to employ one of the strategies discussed in that paper so that this state is represented as an electrical node rather than a variable; variables have to be updated on every iteration.
It's also not a good idea to have the contribution statement (the V(Wts)<+WtsReg;) inside a conditional statement - in fact I'm not sure that's really doing anything useful (so remove the surrounding if() statement).
This thread seems to have become a bit of a dumping ground for questions on hidden state; the forum guidelines ask forum users not to post on the end of old threads to avoid muddying the answers and making it harder for people to find specific answers to specific questions.