Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have a question to ask about BSIM model, I hope it
will not take too much time for you to answer this question. Since now
I am using a BSIM3.3 0.18-um CMOS model in my work (Cadence, Spectre)
and I am wondering about how to figure out the total parasitic
capacitances of a transistor. In PSPICE, after I ran a simulation and
click on the Probe window to see the output file, I can see a list of
small-signal parameters saying that, for example, Cgs = 10 fF (for
intrinsic), Cgsov = 20 fF (for overlap capacitance), etc.
However, for BSIM3.3 and for Spectre simulator, I received a set of
small-signal parameters after running a simulation, for example, as
shown in the attached file. For these parameters, for the capacitances,
I don't know how to calculate the total intrinsic and extrinsic
capacitances since they are separated into several capacitances. Would
you mind to explain me a little bit about this ?
The complete set of spectre BSIM3v3 output operating point parameters can be found in the "Virtuoso Simulator Circuit Components and Device Models Manual"
After performing a DC operating point simulation and saving the results, you can use the results browser to select the dcOpInfo (or use print) and browse the available operating point information for a selected component. In my case, I do see "cgs" and "cgsovl" for BSIM3v3
In reply to Jim McMahon:
Thank you very much for the information. I am having a look at the document you mentioned. However, it seems that I am not being able to figure out how to calculate the real intrinsic Cgs, for example. Did you really see Cgs, Cgsov parameters like this from Results --> Print --> DC operating point ?? For my case, as shown in the attached picture, my Cgs is negative and there are also Cgg, Csg, Cdd .., etc. So from this output data, I am very confused about how to calculate the effective value of, for example, intrinsic Cgs.
Would you mind to suggest again :)
In reply to Dancing Wave:
You can refer to these links for explanations of the capacitances in BSIM model:
What version of spectre/MMSIM are you using? I am using spectre 7.1 (a fairly recent version) and get the following from Results --> Print --> DC operating point
signal OP("/I0/NM10" "??")
betaeff 282.703mcbb 50.9655fcbd -77.4215acbdbi 36.8578fcbg -24.7584fcbs -26.1297fcbsbi 48.289fcdb -4.34466acdd 36.929fcddbi -36.9323fcdg -36.9404fcds 15.8045acgb -24.097fcgbovl 265.891acgd -36.5642fcgdovl 36.926fcgg 186.958fcgs -126.297fcgsovl 36.926fcjd 36.9353fcjs 74.4187fcsb -26.8642fcsd -287.387acsg -125.259fcss 152.411fgbd 61.5137u...etc.
In reply to tkhan:
Thank you for the information. Actually, I already knew the meaning of negative capacitances. However, what I have never known is how to calculate the "effecitve" value of the capaictances. For example, in case that I would like to know the total intrinsic gate-source capacitance from the operating-point results, how could I do that ??? There are Cgs, Csg, Css, Cgg ... etc. How could I calculate the total Cgs using these parameters ???
By the way, thank you very much again,
Thank you for the reply and for the data. Yes, I also have something look like this from my operating point list. However, I am curious about how to calculate the total, for example, Cgs. As you can see from your op list, there are Cgs (which I am not sure that if it is the total intrinsic Cgs), Csg, Cgg, Css ... etc. Cgsovl seems to be reasonable to be the overlap capacitance between the gate and the source. However, what about Cgs ???
Thank you very much for your reply again,
Cgs, Cgd, C[i,j] etc. are the total intrinsic capacitances. See the chapter 4 of the specific version of the BSIM model you are using for the charge equations. This chapter also should describe the extrinsic capacitances such as gate overlap capacitance.
Thank you for your information. I have downloaded the document and checked it. Yes, Ci,j in the document means the intrinsic capacitance of each terminal corresponding to the equation Ci,j = dQi/dVj. However, if we would like to calculate, for example, the total intrinsic capacitance between the gate and the source and what we can find from the operating point result are Cgs, Csg, Cgg and Css. I am still wondering how to use these values in the calculation of Cgs_tot ... I am not sure if I can use the absolute value of Cgs or Csg directly (there values even not the same). Then, what about Cgg and Css ... I have not found any document stating about this calculation. But I am still digging into it.
Thank you for your reply again,
As far as I know, that is why there is a captab option in spectre. It can be used together with dc simulation or transient simulation at certain points.
It gives you fairly, what you want...
In reply to first:
hi everybody....i want to calculate the node capacitance of digital circuit(eg.adder cmos), and i have done "captab" analysis in spectre.....which gave the table listing capacitance of node, node to ground,node to node of every drain,source,gate terminal....but i am confused whether it is total capacitance(diffusion,intrinsic,extrinsic,node capacitanc due to other).... .