Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I had a question, which is not related to the topic.
I was trying to extract name of instance from layout XL, and every instnace has a " | " in starting eg. "|M1". Now when i was trying to save the name as inst~>name, it saves as " "|M1" ", i.e with quotation. Is there a way to convert this string to symbol. i need just |M1.
i had a case where the inst name was " "|M1.1" " also.
If it is not related to the topic, you should really
create a new thread (as the Forum Guidelines tell you to do). So I split it into a new thread to avoid confusion.
don't understand - are you saying that the instance names have embedded
quotation marks? That sounds very odd, and I've not seen that before.
You can of course convert a string to a symbol (e.g. with stringToSymbol() ), but I somehow doubt you really want to do that.
I think the "ParseString()" would be helpful.
here is a skill code ,maybe it will help you.
/*Synopsis : CreateXL_Label()Version : 1.0Create Date : 2007-09-13Author : Justin WangE-Mail : firstname.lastname@example.org*/hiSetBindKey("Layout" "Ctrl<Key>l" "CreateXL_Label()")procedure(CreateXL_Label()prog((winId cvId Shapes Layer shp Box llx lly urx ury Text)winId = hiGetCurrentWindow()cvId = getEditRep(winId)Shapes = geGetSelSet(cvId)Layer = list("TEXT" "drawing")foreach(shp Shapesif((shp~>objType == "inst" ) thenBox = shp~>bBoxllx = car(car(Box))lly = cadr(car(Box))urx = car(cadr(Box))ury = cadr(cadr(Box))Text = car(parseString(shp~>name)); example: |M36.1 ---> |M36.1
;Text = car(parseString(shp~>name "|")); example: |M36.1 ---> |M36.1
;Text = car(parseString(shp~>name "|.")); example: |M36.1 ---> M36if((urx-llx < ury-lly) thendbCreateLabel(cvId Layer (llx+urx)/2:(lly+ury)/2Text "centerCenter" "R90" "stick" (ury-11y)/10 )elsedbCreateLabel(cvId Layer (llx+urx)/2:(lly+ury)/2Text "centerCenter" "R0" "stick" (urx-llx)/10 ));if);if);foreach);prog);procedure