Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I want to stretch and connect two paths which are apart by less than a fixed spacing(say 0.003 micron). This is needed because while doing dbLayerTile(), the newly created rectangles, which were part of the same polygon sometime tend to be cut apart by 0.003 u or so.
Any idea on how to implement this?
What subversion of virtuoso are you using? (Do help->About in the CIW). There was an issue at one point where the dbLayer functions were snapping to the mfg grid - this was later changed back, and an optional argument added to allow gridding to be performed if needed (see Cadence Online Support Solution 11481956 for more details).
Otherwise I can't see why you'd end up with these small gaps. Also, dbLayerTile produces rectangles/polygons, yet you're talking about paths - I assume this must be related to your other similar post?
Anyway, the best solution is to try to prevent these gaps from happening in the first place. It seems a little odd that there are 0.003 spaced gaps - is the data not on grid in the first place?