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  3. PSpice netlist, no ground net problem

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PSpice netlist, no ground net problem

LegendofPedro
LegendofPedro over 12 years ago

I'm having serious problems modelling the infinite resistor grid problem. When creating a PSpice netlist from OrCAD I am being told that I haven't included a ground net. However, I have added plenty of ground symbols (Place->Ground) and have ensured that the net name is "0".

Any ideas about what's going wrong here?

Regards,
Pedro

OrCAD/pspice error

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  • LegendofPedro
    LegendofPedro over 12 years ago

    Apparently an update is out of the question.

    I've tried multiple simulation profiles but I always get a netlist generated like the one included below. No matter how or where I add GND symbols, no 0 net appears in the output file.


    **** 10/17/13 17:24:36 ******* PSpice 16.3.0 (June 2009) ****** ID# 0 ********

     ** Profile: "inf-prof2"  [ J:\My_Documents\L4\CAD in Electronics\Workshop 1B\r-networks-PSpiceFiles\inf\prof2.sim ]


     ****     CIRCUIT DESCRIPTION


    ******************************************************************************


    ** Creating circuit file "prof2.cir"
    ** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

    *Libraries:
    * Profile Libraries :
    * Local Libraries :
    * From [PSPICE NETLIST] section of C:\Cadence\SPB_16.3\tools\PSpice\PSpice.ini file:
    .lib "nom.lib"

    *Analysis directives:
    .TRAN  0 1000ns 0
    .PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
    .INC "..\inf.net"

    **** INCLUDING inf.net ****
    * source R-NETWORKS
    R_b9_R4         N01668 N01652  1 TC=0,0
    R_b9_R8         N01668 N01588  1 TC=0,0
    R_b9_R1         N01728 N01660  1 TC=0,0
    R_b9_R5         N01728 N01728  1 TC=0,0
    R_b9_R2         N01660 N01664  1 TC=0,0
    R_b9_R6         N01660 N01580  1 TC=0,0
    R_b9_R3         N01664 N01668  1 TC=0,0
    R_b9_R7         N01664 N01584  1 TC=0,0
    R_b8_R4         N01640 N01728  1 TC=0,0
    R_b8_R8         N01640 N01572  1 TC=0,0
    R_b8_R1         N01624 N01632  1 TC=0,0
    R_b8_R5         N01624 N01556  1 TC=0,0
    R_b8_R2         N01632 N01636  1 TC=0,0
    R_b8_R6         N01632 N01564  1 TC=0,0
    R_b8_R3         N01636 N01640  1 TC=0,0
    R_b8_R7         N01636 N01568  1 TC=0,0
    R_b10_R4         N01684 N01648  1 TC=0,0
    R_b10_R8         N01684 N01604  1 TC=0,0
    R_b10_R1         N01652 N01676  1 TC=0,0
    R_b10_R5         N01652 N01486  1 TC=0,0
    R_b10_R2         N01676 N01680  1 TC=0,0
    R_b10_R6         N01676 N01596  1 TC=0,0
    R_b10_R3         N01680 N01684  1 TC=0,0
    R_b10_R7         N01680 N01600  1 TC=0,0
    R_b5_R4         N01588 N01486  1 TC=0,0
    R_b5_R8         N01588 N01478  1 TC=0,0
    R_b5_R1         N01728 N01580  1 TC=0,0
    R_b5_R5         N01728 N01728  1 TC=0,0
    R_b5_R2         N01580 N01584  1 TC=0,0
    R_b5_R6         N01580 N01470  1 TC=0,0
    R_b5_R3         N01584 N01588  1 TC=0,0
    R_b5_R7         N01584 N01474  1 TC=0,0
    R_b14_R4         N01728 N01728  1 TC=0,0
    R_b14_R8         N01728 N01684  1 TC=0,0
    R_b14_R1         N01728 N01728  1 TC=0,0
    R_b14_R5         N01728 N01652  1 TC=0,0
    R_b14_R2         N01728 N01728  1 TC=0,0
    R_b14_R6         N01728 N01676  1 TC=0,0
    R_b14_R3         N01728 N01728  1 TC=0,0
    R_b14_R7         N01728 N01680  1 TC=0,0
    R_b1_R4         N01478 N01482  1 TC=0,0
    R_b1_R8         N01478 N01768  1 TC=0,0
    R_b1_R1         N01728 N01470  1 TC=0,0
    R_b1_R5         N01728 N01768  1 TC=0,0
    R_b1_R2         N01470 N01474  1 TC=0,0
    R_b1_R6         N01470 N01768  1 TC=0,0
    R_b1_R3         N01474 N01478  1 TC=0,0
    R_b1_R7         N01474 N01768  1 TC=0,0
    R_b6_R4         N01604 N01764  1 TC=0,0
    R_b6_R8         N01604 N01532  1 TC=0,0
    R_b6_R1         N01486 N01596  1 TC=0,0
    R_b6_R5         N01486 N01482  1 TC=0,0
    R_b6_R2         N01596 N01600  1 TC=0,0
    R_b6_R6         N01596 N01524  1 TC=0,0
    R_b6_R3         N01600 N01604  1 TC=0,0
    R_b6_R7         N01600 N01528  1 TC=0,0
    R_b15_R4         N01728 N01728  1 TC=0,0
    R_b15_R8         N01728 N01700  1 TC=0,0
    R_b15_R1         N01728 N01728  1 TC=0,0
    R_b15_R5         N01728 N01648  1 TC=0,0
    R_b15_R2         N01728 N01728  1 TC=0,0
    R_b15_R6         N01728 N01692  1 TC=0,0
    R_b15_R3         N01728 N01728  1 TC=0,0
    R_b15_R7         N01728 N01696  1 TC=0,0
    R_b12_R4         N01716 N01728  1 TC=0,0
    R_b12_R8         N01716 N01640  1 TC=0,0
    R_b12_R1         N01644 N01708  1 TC=0,0
    R_b12_R5         N01644 N01624  1 TC=0,0
    R_b12_R2         N01708 N01712  1 TC=0,0
    R_b12_R6         N01708 N01632  1 TC=0,0
    R_b12_R3         N01712 N01716  1 TC=0,0
    R_b12_R7         N01712 N01636  1 TC=0,0
    R_b7_R4         N01620 N01624  1 TC=0,0
    R_b7_R8         N01620 N01552  1 TC=0,0
    R_b7_R1         N01764 N01612  1 TC=0,0
    R_b7_R5         N01764 N01536  1 TC=0,0
    R_b7_R2         N01612 N01616  1 TC=0,0
    R_b7_R6         N01612 N01544  1 TC=0,0
    R_b7_R3         N01616 N01620  1 TC=0,0
    R_b7_R7         N01616 N01548  1 TC=0,0
    R_b16_R4         N01728 N01728  1 TC=0,0
    R_b16_R8         N01728 N01716  1 TC=0,0
    R_b16_R1         N01728 N01728  1 TC=0,0
    R_b16_R5         N01728 N01644  1 TC=0,0
    R_b16_R2         N01728 N01728  1 TC=0,0
    R_b16_R6         N01728 N01708  1 TC=0,0
    R_b16_R3         N01728 N01728  1 TC=0,0
    R_b16_R7         N01728 N01712  1 TC=0,0
    V_V1         N01768 N01728 1Vdc
    R_b11_R4         N01700 N01644  1 TC=0,0
    R_b11_R8         N01700 N01620  1 TC=0,0
    R_b11_R1         N01648 N01692  1 TC=0,0
    R_b11_R5         N01648 N01764  1 TC=0,0
    R_b11_R2         N01692 N01696  1 TC=0,0
    R_b11_R6         N01692 N01612  1 TC=0,0
    R_b11_R3         N01696 N01700  1 TC=0,0
    R_b11_R7         N01696 N01616  1 TC=0,0
    R_b13_R4         N01728 N01728  1 TC=0,0
    R_b13_R8         N01728 N01668  1 TC=0,0
    R_b13_R1         N01728 N01728  1 TC=0,0
    R_b13_R5         N01728 N01728  1 TC=0,0
    R_b13_R2         N01728 N01728  1 TC=0,0
    R_b13_R6         N01728 N01660  1 TC=0,0
    R_b13_R3         N01728 N01728  1 TC=0,0
    R_b13_R7         N01728 N01664  1 TC=0,0
    R_b4_R4         N01572 N01728  1 TC=0,0
    R_b4_R8         N01572 N01776  1 TC=0,0
    R_b4_R1         N01556 N01564  1 TC=0,0
    R_b4_R5         N01556 N01776  1 TC=0,0
    R_b4_R2         N01564 N01568  1 TC=0,0
    R_b4_R6         N01564 N01776  1 TC=0,0
    R_b4_R3         N01568 N01572  1 TC=0,0
    R_b4_R7         N01568 N01776  1 TC=0,0
    R_b3_R4         N01552 N01556  1 TC=0,0
    R_b3_R8         N01552 N01772  1 TC=0,0
    R_b3_R1         N01536 N01544  1 TC=0,0
    R_b3_R5         N01536 N01772  1 TC=0,0
    R_b3_R2         N01544 N01548  1 TC=0,0
    R_b3_R6         N01544 N01772  1 TC=0,0
    R_b3_R3         N01548 N01552  1 TC=0,0
    R_b3_R7         N01548 N01772  1 TC=0,0
    R_b2_R4         N01532 N01536  1 TC=0,0
    R_b2_R8         N01532 N01804  1 TC=0,0
    R_b2_R1         N01482 N01524  1 TC=0,0
    R_b2_R5         N01482 N01804  1 TC=0,0
    R_b2_R2         N01524 N01528  1 TC=0,0
    R_b2_R6         N01524 N01804  1 TC=0,0
    R_b2_R3         N01528 N01532  1 TC=0,0
    R_b2_R7         N01528 N01804  1 TC=0,0

    **** RESUMING prof2.cir ****
    .END

    ERROR -- Node N01668 is floating
    ERROR -- Node N01652 is floating
    ERROR -- Node N01588 is floating
    ERROR -- Node N01728 is floating
    ERROR -- Node N01660 is floating
    ERROR -- Node N01664 is floating
    ERROR -- Node N01580 is floating
    ERROR -- Node N01584 is floating
    ERROR -- Node N01640 is floating
    ERROR -- Node N01572 is floating
    ERROR -- Node N01624 is floating
    ERROR -- Node N01632 is floating
    ERROR -- Node N01556 is floating
    ERROR -- Node N01636 is floating
    ERROR -- Node N01564 is floating
    ERROR -- Node N01568 is floating
    ERROR -- Node N01684 is floating
    ERROR -- Node N01648 is floating
    ERROR -- Node N01604 is floating
    ERROR -- Node N01676 is floating
    ERROR -- Node N01486 is floating
    ERROR -- Node N01680 is floating
    ERROR -- Node N01596 is floating
    ERROR -- Node N01600 is floating
    ERROR -- Node N01478 is floating
    ERROR -- Node N01470 is floating
    ERROR -- Node N01474 is floating
    ERROR -- Node N01482 is floating
    ERROR -- Node N01768 is floating
    ERROR -- Node N01764 is floating
    ERROR -- Node N01532 is floating
    ERROR -- Node N01524 is floating
    ERROR -- Node N01528 is floating
    ERROR -- Node N01700 is floating
    ERROR -- Node N01692 is floating
    ERROR -- Node N01696 is floating
    ERROR -- Node N01716 is floating
    ERROR -- Node N01644 is floating
    ERROR -- Node N01708 is floating
    ERROR -- Node N01712 is floating
    ERROR -- Node N01620 is floating
    ERROR -- Node N01552 is floating
    ERROR -- Node N01612 is floating
    ERROR -- Node N01536 is floating
    ERROR -- Node N01616 is floating
    ERROR -- Node N01544 is floating
    ERROR -- Node N01548 is floating
    ERROR -- Node N01776 is floating
    ERROR -- Node N01772 is floating
    ERROR -- Node N01804 is floating

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  • LegendofPedro
    LegendofPedro over 12 years ago

    Apparently an update is out of the question.

    I've tried multiple simulation profiles but I always get a netlist generated like the one included below. No matter how or where I add GND symbols, no 0 net appears in the output file.


    **** 10/17/13 17:24:36 ******* PSpice 16.3.0 (June 2009) ****** ID# 0 ********

     ** Profile: "inf-prof2"  [ J:\My_Documents\L4\CAD in Electronics\Workshop 1B\r-networks-PSpiceFiles\inf\prof2.sim ]


     ****     CIRCUIT DESCRIPTION


    ******************************************************************************


    ** Creating circuit file "prof2.cir"
    ** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

    *Libraries:
    * Profile Libraries :
    * Local Libraries :
    * From [PSPICE NETLIST] section of C:\Cadence\SPB_16.3\tools\PSpice\PSpice.ini file:
    .lib "nom.lib"

    *Analysis directives:
    .TRAN  0 1000ns 0
    .PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
    .INC "..\inf.net"

    **** INCLUDING inf.net ****
    * source R-NETWORKS
    R_b9_R4         N01668 N01652  1 TC=0,0
    R_b9_R8         N01668 N01588  1 TC=0,0
    R_b9_R1         N01728 N01660  1 TC=0,0
    R_b9_R5         N01728 N01728  1 TC=0,0
    R_b9_R2         N01660 N01664  1 TC=0,0
    R_b9_R6         N01660 N01580  1 TC=0,0
    R_b9_R3         N01664 N01668  1 TC=0,0
    R_b9_R7         N01664 N01584  1 TC=0,0
    R_b8_R4         N01640 N01728  1 TC=0,0
    R_b8_R8         N01640 N01572  1 TC=0,0
    R_b8_R1         N01624 N01632  1 TC=0,0
    R_b8_R5         N01624 N01556  1 TC=0,0
    R_b8_R2         N01632 N01636  1 TC=0,0
    R_b8_R6         N01632 N01564  1 TC=0,0
    R_b8_R3         N01636 N01640  1 TC=0,0
    R_b8_R7         N01636 N01568  1 TC=0,0
    R_b10_R4         N01684 N01648  1 TC=0,0
    R_b10_R8         N01684 N01604  1 TC=0,0
    R_b10_R1         N01652 N01676  1 TC=0,0
    R_b10_R5         N01652 N01486  1 TC=0,0
    R_b10_R2         N01676 N01680  1 TC=0,0
    R_b10_R6         N01676 N01596  1 TC=0,0
    R_b10_R3         N01680 N01684  1 TC=0,0
    R_b10_R7         N01680 N01600  1 TC=0,0
    R_b5_R4         N01588 N01486  1 TC=0,0
    R_b5_R8         N01588 N01478  1 TC=0,0
    R_b5_R1         N01728 N01580  1 TC=0,0
    R_b5_R5         N01728 N01728  1 TC=0,0
    R_b5_R2         N01580 N01584  1 TC=0,0
    R_b5_R6         N01580 N01470  1 TC=0,0
    R_b5_R3         N01584 N01588  1 TC=0,0
    R_b5_R7         N01584 N01474  1 TC=0,0
    R_b14_R4         N01728 N01728  1 TC=0,0
    R_b14_R8         N01728 N01684  1 TC=0,0
    R_b14_R1         N01728 N01728  1 TC=0,0
    R_b14_R5         N01728 N01652  1 TC=0,0
    R_b14_R2         N01728 N01728  1 TC=0,0
    R_b14_R6         N01728 N01676  1 TC=0,0
    R_b14_R3         N01728 N01728  1 TC=0,0
    R_b14_R7         N01728 N01680  1 TC=0,0
    R_b1_R4         N01478 N01482  1 TC=0,0
    R_b1_R8         N01478 N01768  1 TC=0,0
    R_b1_R1         N01728 N01470  1 TC=0,0
    R_b1_R5         N01728 N01768  1 TC=0,0
    R_b1_R2         N01470 N01474  1 TC=0,0
    R_b1_R6         N01470 N01768  1 TC=0,0
    R_b1_R3         N01474 N01478  1 TC=0,0
    R_b1_R7         N01474 N01768  1 TC=0,0
    R_b6_R4         N01604 N01764  1 TC=0,0
    R_b6_R8         N01604 N01532  1 TC=0,0
    R_b6_R1         N01486 N01596  1 TC=0,0
    R_b6_R5         N01486 N01482  1 TC=0,0
    R_b6_R2         N01596 N01600  1 TC=0,0
    R_b6_R6         N01596 N01524  1 TC=0,0
    R_b6_R3         N01600 N01604  1 TC=0,0
    R_b6_R7         N01600 N01528  1 TC=0,0
    R_b15_R4         N01728 N01728  1 TC=0,0
    R_b15_R8         N01728 N01700  1 TC=0,0
    R_b15_R1         N01728 N01728  1 TC=0,0
    R_b15_R5         N01728 N01648  1 TC=0,0
    R_b15_R2         N01728 N01728  1 TC=0,0
    R_b15_R6         N01728 N01692  1 TC=0,0
    R_b15_R3         N01728 N01728  1 TC=0,0
    R_b15_R7         N01728 N01696  1 TC=0,0
    R_b12_R4         N01716 N01728  1 TC=0,0
    R_b12_R8         N01716 N01640  1 TC=0,0
    R_b12_R1         N01644 N01708  1 TC=0,0
    R_b12_R5         N01644 N01624  1 TC=0,0
    R_b12_R2         N01708 N01712  1 TC=0,0
    R_b12_R6         N01708 N01632  1 TC=0,0
    R_b12_R3         N01712 N01716  1 TC=0,0
    R_b12_R7         N01712 N01636  1 TC=0,0
    R_b7_R4         N01620 N01624  1 TC=0,0
    R_b7_R8         N01620 N01552  1 TC=0,0
    R_b7_R1         N01764 N01612  1 TC=0,0
    R_b7_R5         N01764 N01536  1 TC=0,0
    R_b7_R2         N01612 N01616  1 TC=0,0
    R_b7_R6         N01612 N01544  1 TC=0,0
    R_b7_R3         N01616 N01620  1 TC=0,0
    R_b7_R7         N01616 N01548  1 TC=0,0
    R_b16_R4         N01728 N01728  1 TC=0,0
    R_b16_R8         N01728 N01716  1 TC=0,0
    R_b16_R1         N01728 N01728  1 TC=0,0
    R_b16_R5         N01728 N01644  1 TC=0,0
    R_b16_R2         N01728 N01728  1 TC=0,0
    R_b16_R6         N01728 N01708  1 TC=0,0
    R_b16_R3         N01728 N01728  1 TC=0,0
    R_b16_R7         N01728 N01712  1 TC=0,0
    V_V1         N01768 N01728 1Vdc
    R_b11_R4         N01700 N01644  1 TC=0,0
    R_b11_R8         N01700 N01620  1 TC=0,0
    R_b11_R1         N01648 N01692  1 TC=0,0
    R_b11_R5         N01648 N01764  1 TC=0,0
    R_b11_R2         N01692 N01696  1 TC=0,0
    R_b11_R6         N01692 N01612  1 TC=0,0
    R_b11_R3         N01696 N01700  1 TC=0,0
    R_b11_R7         N01696 N01616  1 TC=0,0
    R_b13_R4         N01728 N01728  1 TC=0,0
    R_b13_R8         N01728 N01668  1 TC=0,0
    R_b13_R1         N01728 N01728  1 TC=0,0
    R_b13_R5         N01728 N01728  1 TC=0,0
    R_b13_R2         N01728 N01728  1 TC=0,0
    R_b13_R6         N01728 N01660  1 TC=0,0
    R_b13_R3         N01728 N01728  1 TC=0,0
    R_b13_R7         N01728 N01664  1 TC=0,0
    R_b4_R4         N01572 N01728  1 TC=0,0
    R_b4_R8         N01572 N01776  1 TC=0,0
    R_b4_R1         N01556 N01564  1 TC=0,0
    R_b4_R5         N01556 N01776  1 TC=0,0
    R_b4_R2         N01564 N01568  1 TC=0,0
    R_b4_R6         N01564 N01776  1 TC=0,0
    R_b4_R3         N01568 N01572  1 TC=0,0
    R_b4_R7         N01568 N01776  1 TC=0,0
    R_b3_R4         N01552 N01556  1 TC=0,0
    R_b3_R8         N01552 N01772  1 TC=0,0
    R_b3_R1         N01536 N01544  1 TC=0,0
    R_b3_R5         N01536 N01772  1 TC=0,0
    R_b3_R2         N01544 N01548  1 TC=0,0
    R_b3_R6         N01544 N01772  1 TC=0,0
    R_b3_R3         N01548 N01552  1 TC=0,0
    R_b3_R7         N01548 N01772  1 TC=0,0
    R_b2_R4         N01532 N01536  1 TC=0,0
    R_b2_R8         N01532 N01804  1 TC=0,0
    R_b2_R1         N01482 N01524  1 TC=0,0
    R_b2_R5         N01482 N01804  1 TC=0,0
    R_b2_R2         N01524 N01528  1 TC=0,0
    R_b2_R6         N01524 N01804  1 TC=0,0
    R_b2_R3         N01528 N01532  1 TC=0,0
    R_b2_R7         N01528 N01804  1 TC=0,0

    **** RESUMING prof2.cir ****
    .END

    ERROR -- Node N01668 is floating
    ERROR -- Node N01652 is floating
    ERROR -- Node N01588 is floating
    ERROR -- Node N01728 is floating
    ERROR -- Node N01660 is floating
    ERROR -- Node N01664 is floating
    ERROR -- Node N01580 is floating
    ERROR -- Node N01584 is floating
    ERROR -- Node N01640 is floating
    ERROR -- Node N01572 is floating
    ERROR -- Node N01624 is floating
    ERROR -- Node N01632 is floating
    ERROR -- Node N01556 is floating
    ERROR -- Node N01636 is floating
    ERROR -- Node N01564 is floating
    ERROR -- Node N01568 is floating
    ERROR -- Node N01684 is floating
    ERROR -- Node N01648 is floating
    ERROR -- Node N01604 is floating
    ERROR -- Node N01676 is floating
    ERROR -- Node N01486 is floating
    ERROR -- Node N01680 is floating
    ERROR -- Node N01596 is floating
    ERROR -- Node N01600 is floating
    ERROR -- Node N01478 is floating
    ERROR -- Node N01470 is floating
    ERROR -- Node N01474 is floating
    ERROR -- Node N01482 is floating
    ERROR -- Node N01768 is floating
    ERROR -- Node N01764 is floating
    ERROR -- Node N01532 is floating
    ERROR -- Node N01524 is floating
    ERROR -- Node N01528 is floating
    ERROR -- Node N01700 is floating
    ERROR -- Node N01692 is floating
    ERROR -- Node N01696 is floating
    ERROR -- Node N01716 is floating
    ERROR -- Node N01644 is floating
    ERROR -- Node N01708 is floating
    ERROR -- Node N01712 is floating
    ERROR -- Node N01620 is floating
    ERROR -- Node N01552 is floating
    ERROR -- Node N01612 is floating
    ERROR -- Node N01536 is floating
    ERROR -- Node N01616 is floating
    ERROR -- Node N01544 is floating
    ERROR -- Node N01548 is floating
    ERROR -- Node N01776 is floating
    ERROR -- Node N01772 is floating
    ERROR -- Node N01804 is floating

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