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OpAmp Simulation in Cadence Spectre

Shahnaf
Hi, I have used OpAmp symbol from Solutions library (default library of cadence). As an initial step, I have simulated a basic circuit in Op Amp. But I am not getting the desired output. Moreover, I have checked the cadence simulation manual for Op Amp. I found something difference in the symbol (from Solutions library) to that of the Cadence manual. Can you please let me know where I am wrong and what needs to be corrected? Thanks, Shahnaz

  • I'm not sure what your objection to a Verilog-A model is, but regardless of this, the issue is not really down to the model but to do with the fact that your circuit is saturating in the DC operating point and will take a really long time to recover. During the DC operating point, the capacitance is removed, and  the gain will be pretty much set by the 100000 you have set (I think there will be a 1Tohm gmin resistance across the capacitor even if you don't put one there). So I get an output at about 40kV from my netlist-based design

    //
    V0 (sig 0) vsource type=pulse val0=0.5 val1=1.3 rise=1n period=100n width=50n
    V11 (inp 0) vsource dc=0.9
    R0 (sig inm) resistor r=10k
    C0 (inm out) capacitor c=5p
    //R1 (inm out) resistor r=100k
    E1 (out 0 inp inm) vcvs gain=100000

    tran tran stop=50u

    If I uncomment the resistor (a much more reasonable resistor value), it's much easier to see what's going on (my pulse source is probably different from yours because I didn't know the parameters you used), but nevertheless you can see what's happening:

    The picture on the right is a zoom-in on the output signal - as you can see, it's integrating the square wave input nicely. On the left however, you can see that it is saturating at time zero. 

    So I suspect this is what you are seeing - the opamp is virtually open-loop at DC.

    Regards,

    Andrew.

  • Oh, and by the way, the Guidelines for the RF Design Forum ask you not to post on the end of an old thread.

    Regards,

    Andrew.

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