expression problem from ac sweep

Unknown said:

If you are trying to measure the current through your entire varactor network, the current probe can be placed in series with the gate of the drain-source connected MOS device. Remove the 100K resistor totally. The probe will then capture all the current through the drain-source connected device and the switched capacitors.

Hello i have changed the circuit and the simulation as you said with the expression shown bellow.

i added a 1A ac source and 1mH  inductor in series with the VVDC source.

in the results of the formula it gives a constant capacitance no matter what VVDC voltage .

where in the AC current source did i got wrong? 

another problem is why we dont calculate the capacitance from the OUT node signed in red?

the VCO will look at the capacitance from that point,so we do need to put the iprobe there and VOUT there

am  i correct?

Thanks

(-1 / (2 * 1e+09 * value(imag(v("/vout" ?result "ac") / i("/IPRB0/PLUS" ?result "ac")) 1e+09) * pi))

Dear Yefl,

> in the results of the formula it gives a constant capacitance no matter what VVDC voltage .

> where in the AC current source did i got wrong?

You did not set the DC potential at your top node vout to be anything. Hence, it is floating and will take on the same value as your applied control voltage (vvdc). Hence, there will be no change in capacitance as you change the control voltage vvdc.

> another problem is why we dont calculate the capacitance from the OUT node signed in red?

> the VCO will look at the capacitance from that point,so we do need to put the iprobe there and VOUT there

> am  i correct?

I was wondering where the VCO node was. Please use the circuit shown in the attached file to measure the capacitance as a function of your control voltage:

Shawn

Hello , i have made the test bench as you described and i got results.

but in our VCO as shown bellow there is no ac current source,so how it's equivalent regarding the impedance that it will present in the actual system? 

another thing is how do you suggest connecting it to the VCO?   in our varactor there is no "two sides" as in the capactior shown in the schematics bellow. 

Thanks.

Dear yejf,

> but in our VCO as shown bellow there is no ac current source,so how it's equivalent regarding

> the impedance that it will present in the actual system?

The impedance you are supposed to simulate is the impedance that the inductor will see. The impedance you are computing is from  node v_vco to ground. If that is the impedance the inductor will see in your VCO, that is the correct impedance to simulate.

> in our varactor there is no "two sides" as in the capactior shown in the schematics bellow. 

I do not understand how the varactor will vary its capacitance in your VCO circuit as there is no DC isolation of its bottom terminal from its top terminal. You can only change its capacitance with a change in DC voltage across the varactor. You need to include an AC coupling capacitor if you do not have a means to isolate the DC voltage of your varactor bottom terminal.

I think you need to study other VCO designs in the literature as it appears your design and the capacitance voltage characteristic you plot need some design effort. Is this a school project or an actual design? This forum is focused on solving Cadence related issues.

Shawn

Hello Shawn and Andrew, thank you very much , i got a good varactor exactly as you described in you test bench methodics.