cadence gpdk45 off grid problem

When you select another error, use the right arrow in the UI to visit each of the errors. The pair of left/right errors next to the AV/NV buttons visit the next error on the current rule. The left/right arrows to the right of the Cell Filter visit the next/previous error in the current cell (the tooltips over the arrows tell you this). Just clicking on the next error line doesn't show you where they are - you need to visit each. So it's nothing to do with the error being in the transistor - just that you're probably not actually hitting the correct button...

If you have a minimum size device, the height of the nwell on the pmos at the top will be too narrow and less than the minimum width. There is nothing to stop you drawing a rectangle of nwell over the transistor which is greater than 0.3um wide (or high) so that you meet that rule. Each device does not guarantee to meet all the design rules in isolation - if the pcell draw an nwell shape larger than needed for the overlaps, it would limit you because if the additional nwell needed to meet the rule was above or below the transistor, it might not be where you want - whereas if you can draw it yourself, you have more flexibility.

It's not that common to solely have a single minimum sized device in a well - usually you would share the well with other devices, and it's then easy to ensure that such minimum rules are met.

I really think you need to talk to your supervisor about all these questions because this forum cannot be a means to teach you how to do IC layout!

Regards,

Andrew.

Hello Andrew ,is there a document about the gpdk45 that talks about its DRC standards? 

so i could interpret those layer size errors.
i tried to search for one and couldnt find a document that actually describes each DRC rule and how it should look,it would be very helpfull.
Thanks .

This is in gpdk045 v5.0 :

UNIX> ls $KITHOME
assura/ diva/ gpdk045/ libManager.log pvs/ soce/
assura_tech.lib* docs/ gpdk045.tf models/ pvtech.lib*
cds.lib dumpit.cdf lib.defs pmos1v.cdf qrc/
UNIX> ls $KITHOME/docs
RELEASE_NOTES gpdk045_PDK_Model_Report.pdf gpdk045_pdk_referenceManual.pdf
VERSION gpdk045_drc.pdf

The gpdk045_drc.pdf is the document that describes the design rules - quite clearly.

Regards,

Andrew.

Hello Andrew, i tried to follow you direction.i get undefined variable problem as shown in the print screen bellow.
is there some link from the Cadence website i can use?
Anyway Thank you very much for the guidance.

Oh, please don't take what I said quite so literally. This is getting to be hard work... I just happened to have $KITHOME pointing at where my gpdk045 installation is (for convenience). I wasn't expecting you to have it set the same way. I was assuming  you'd be able to locate where gpdk045 is installed and look for the similar directory.

In the CIW, you could do:

ddGetObj("gpdk045")~>readPath

This will return something like (the path is probably completely different in  your environment):

"/export/home/myuser/kits/gpdk045_v_5_0/gpdk045"

Then if you look in the parent directory (e.g.) /export/home/myuser/kits/gpdk045_v_5_0/ you should see a "docs" subdirectory and the PDF within that.

Regards,

Andrew.

Found it :-) thank you very much for your help.