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Simplifying ratsnest to a connector or FPGA during routing and update the schematic. I shared a Skill script.

Robert Finley

https://community.cadence.com/cadence_technology_forums/f/pcb-skill/47891/skill-method-to-optimize-netlist-pin-assignments-on-components-in-allegro-and-orcad-capture

  • RFinley
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    There is a problem with replaceAlias in the standard capDesignUtil Orcad library.   I depend on searching for nets with a TEMP prefix then replacing them with the final net name.

    This only works if all of the TEMP net aliases have THE SAME LENGTH.   If there are some TEMP alias names of different lengths, Orcad will create new net aliases and add a number.  Not good.

    So, if you have 100 nets to update, need to start with TEMP100, or TEMP1000 alias and increment from there.

    The fix is easy. 

    TEMP aliases are only used for the schematic merge.  Update to new aliases on the schematic, push to layout, re-run the swapback script, then the new update script should update the schematic correctly.

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