Issue trying to add route / via

 Can you please be specific when you indicate something is in the tutorials.  I have been through the tutorials. In particular:

1.  How do you change the default via when from a pin you do "Add connect" then "Add VIA"?

2.  Is there a way to force the route to conform to the electrical spacing rule?  When adding a VIA?

3.  Is there a way to change the net on which a line is on?  For example, if you copy a cline and VIA, can you change it to another net so that it can connect up to a different pin?

I have been repeatably told how much better this tool is from Altium, but there are very simple operations on Altium that I am having trouble configuring Allegro to do.

Specific User Guide information on diff pair issue:  File is algrorouteTOC.html at Your_Install_Directory/doc/algroroute.  After opening the file, do a search on "single trace mode" and follow the links. 

Many other routing basics that you have mentioned can also be found in this document.  Much as I would like to help, I don't have the time to teach you how to use Allegro.  Perhaps taking a class would be a good next step.

 Fair enough.  I was hoping other users that have had these issues would also respond.

 The symptom you have is fairly typical of a setup problem ... probably no surprise at this time.

First, what version are you running?  And what license level?

The VIA problem you describe hints at the physcial constraints not be properly setup.  The fact that not all the pins fanout hint at a spacing constraint setup problem.  The fanout engine respects all constraints on the board and if you overconstrain you can't get the fanout to work.

So one method to investigate the fanout problem is run it in the actual interactive router (Specctra).  You can rip off all of the constraints by running the do file that's generated when  you enter the router (are you familiar with these?).

Once you successfully fanout with the interactive router and come back into Allegro you should run DRC updates and you will probably see hundreds of DRCs caused by a constraint error.

If you want, you can zip up your PCB and post it on here and have someone (myself) take a look.

Bill 

 To answer your first questions, I have the 16.01 release with Performance Option L

When you say VIA problem, as I mentioned before, I have set up the default VIA to be my minimum VIA size, 10 mil hole, 20 mil pad.  This shows up on the Physical on all layers, all nets, all regions.

 I have for the moment resolved the Fanout, since my goal is not to fan out the board, but to determine how close I can place my passives to my BGA parts.  I manually fanned out a single pin and then used the "VIA Structure" method of using it for all the pins.

I could send my file, but I was hoping a list of the steps for doing these operations to be explained in the forum, that way other people could learn from them.  I have been quite disappointed in the content of these forums and was hoping that they would contain more examples. 

So for example, go through the steps for changing the default VIA size for all of the aspects of the design.  That way I can go through the steps myself.