Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top?

Bill,

As far as the Place_bound_top, the post from "Randy R" actually made a very good point that the Place_bound_top is used by the IDF Interface to form the component boundary / height on the Pro-E side so having it extended out to accomidate additional clearance would generate the incorrect component boundary on the Pro-E side.

As far as the Press Fit clearance, I build them into the Package Symbol using Place_bound_top shapes using the recommended tooling from the component manufacturer and of course run this past our Contract Manufacture House to insure that it is acceptable or not.  The CM sometimes wants to save money and create their own press fit tooling but from past experience if they do not have capable folks at the CM it will lead to all types of issues.

As far as the Selective wave clearances, I build them at the Board Level after/during placement activities mainly because I normally group these thru hole components together to share the same Selective wave window to conserve placement space.  These are generated using Package Keepouts top and bottom and YES it is very difficult when placement changes and the Keepouts don't move with the components but I would simply run out of placement space if I did not share the Selective wave keepouts so it is something that must be done at the Board Level.  I have not really found a better way of doing it but this way seems to work for me at least. 

Normally, we only have a Selective Wave keepout on the opposite side of the thru hole component and never had a different clearance from the body of selective wave components. The selective wave clearance is from PTH Pin to SMD Component on Side 2 is the only requirement I need to meet.

Good luck,
Michael Catrambone

PCBGeorge,

Whatever became of your script evaluation?

Bret

Hi Scott,

Very old thread and a lot has changed since then.  Let me try to respond the best way I can.

3D Viewer:
With the release of the 3D viewer (3D Viewer is fairly new functionality), oversized PLACE_BOUND_TOP can make the component view in 3D very misleading, even if the PLACE_BOUND_TOP was sized the exact size of the component. Obviously this is greatly improved with the ability to map a true 3D STEP file to the components so the 3D View is very realistic.

IDF Export to Mechanical Package:
You do have the ability to remap a components 3D representation (3D Box) using a different Package Geometry subclass when exporting an IDF file to a mechanical package but it does not change the way the 3D viewer looks in Allegro. The variables that control this is IDF_PLACE_BOUNDS_TOP and IDF_PLACE_BOARDS_BOTTOM with a value matching the SUBCLASS name under Package Geometry.  During export it will look at these subclasses for shapes to drive the 3D Box instead of the PLACE_BOUND_TOP and PLACE_BOUND_BOTTOM but it doesn't help you with the 3D Viewer.

Component DRC Errors:
The PLACE_BOUND_TOP and PLACE_BOUND_BOTTOM Subclasses will generate a DRC when they come in contact with each other during placement which is one of its main purposes. You could make it smaller to just include the body of the component but you may miss a component to component DRC because of it.  Sure, you may see a Pin to Pin DRC when the pins come in contact with each other but you will not see a DRC on the PACKAGE_TOP and PACKAGE_BOTTOM subclasses.

PACKAGE KEEPOUT defined in symbols:
You have the ability to define a shape on PACKAGE KEEPOUT / TOP in the symbol but when these shapes come in contact with each other during placement they will never show a DRC Error.  A DRC error will only occur when a shape from PACKAGE GEOMETRY / PLACE_BOUND_TOP comes in contact with a shape on PACKAGE KEEPOUT / TOP.

I really don't have an answer for you regarding the results in the 3D Viewer when the PLACE_BOUND_TOP is defined larger than the component but if the PLACE_BOUND_TOP does not include the pins of the device you may miss component to component DRCs during placement.  The original intent for the PLACE_BOUND shapes were to provide a simple way of generating DRCs when two component come in contact with each other.

The other discussion in the thread was the DFA_BOUND_TOP and DFA_BOUND_BOTTOM subclasses, they are used by the real-time DFA checks that are built into Allegro. You develop a spreadsheet of component to component clearances and they will be checked to the DFA_BOUND subclasses.

Sorry for the long response

Hope this helps,
Mike Catrambone

Hi Mike I was thinking of doing some custom symbols and was a little unsure of what would be the best fit with respect to using the PLACE_BOUND_TOP for the footprint. I think using the PLACE_BOUND_TOP keeps with prior versions of Allegro so for me this is a good choice. I will just use it per the original intent but wont bother shaping it so I get a good 3d view.

It is odd that cadence decided to use the PLACE_BOUND_TOP for the 3d view to begin with considering that, that particular class is also used for DRC checking. Believe the idea might have been that since most symbols had a PLACE_BOUND_TOP class defined in the symbol they could use that to build the 3d view from.  

Now the step support in 16.6 is really nice so I think that will handle the 3d in a "big way" going forward.

Thanks for the detailed response it was a big help at this end.

Best regards Scott