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Shape to Route Keepin Spacing

melview1
OrCAD PCB Designer v16.2
 
I am getting the following DRC error, regarding an auto-generated shape (ground or power pours).  I get it on multiple layers with multiple pours:
 
Constraint Name = Shape to Route Keepin Spacing

Required Value = 0 MIL

Actual Value = 0 MIL

Constraint Source = DEFAULT

Constraint Source Type = NET SPACING CONSTRAINTS

Element 1 = Shape(auto-generated) "Gnd, Etch/Inner Signal 2"

Element 2 = Shape "Route Keepin/All"
 
It looks as if my pours go right up to the keepin without any clearance.  This is fine for me since my keepin is pulled back by 25 mils from my board edge.  Reading the DRC error, it looks as if it is adhering to the constraint since the required value is 0 mils and the actual value is 0 mils and there shouldn’t be a DRC error.
 
Does anyone know why this DRC is showing up and/or any settings I can change to make it not appear anymore?  I know I can waive the DRC, but that’s kind of annoying since it happens on multiple designs.  It appears that I can ignore it, but I want to be sure that OrCAD isn’t pointing something out that I am missing.
 
Thanks,

Mark
  • melview1

    @ Steve.  I always add my route_keepin first.  It's usually one of the first things I do.  The issue is still present.  I've deleted shapes and recreated them, using the already present route_keepin and the issue persists.  It looks to be a tolerance/accuracy/rounding thing that OrCAD does incorrectly for some shape angles/arcs.

    I'm open for any, more permanant fixes, but for now, I will use Randy's workaround.

     

    --Mark

  • Boma

    One method we use, instead of chaseing the drc's around the board outline, is to add an oversize clearance value to the shape on the layer that is giviing us problems.  This can also be done globally from the Global Dynamic Shapes Parameters form.  In MM we use a small value like .002 or .004 mm which usually eliminates this issue.

    Boma 

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