How do I make holey (perforated) thermal ground pin?

 I'm also new to Cadence, I'm using Design Entry HDL and Allegro but I think the package creation process is similar. I recently made the exact footprint with the little tabs and x5 thermal vias and I'll try to share my thoughts on the process, as best as I can recall at least.

First, fyi, I didn't use blind vias, I just used a regular via stack-up and I'm assuming that a regular via will be ok.

I broke it down into the elements that went into the final footprint, so:

-made sure that the schematic symbol had an extra (11th) pin named GND that the powerpad will be assigned to.

-made a padstack (.pad) for the 10 regular pins and stored it in my padstack folder

-made a padstack (.pad) for the 3mm vias and stored it in my padstack folder

-made a  shape symbol of the "winged" power pad. this is one single shape, not a collection of rectangles which is another valid way to do it. stored it in my shape or flash folder (can't recall). btw, I used New-->shape, etc... to create it.

-made a padstack (.pad) for the PowerPad and in the BEGIN LAYER and SOLDERMASK_TOP layers, for the "Regular Pad: I chose "Shape" under Geometry, and found the powerPad shape in the location I chose in the previous step. Thermal relief and antipad were Null. All other layers were null. Also, check the "single layer mode" box and of course make sure that the drill size is 0.

-Now, armed with a pin padstack, a via padstack and a powerpad padstack I made a new footprint. Place the pins for pins 1-10 then added an 11th pin, changing the padstack to be the powerpad padstack in the Options menu on the right side. Then I added the vias in the proper location. saved the footprint in my footprint folder.

Now WHY Cadence makes this process so difficult, I have no idea. I think Altium was much easier to use in this respect.

DrL,

Erivas method works very well, but I would add one caution on that process.  You must be careful in creating that power pad shape because of what needs to be exposed copper and what should be covered by solder mask.  If the entire power pad shape is left void of soldermasking, then you may be hard to get the right amount of solder to get a good attachment without it flowing where you don't want it.  This can be handled in the power pad shape creation, but it must be kept in mind.

An alternative method is to make the power pad shape when building the footprint.  Leave all of the standard pads as they are and drop a shape on top of the center pad.  This way, the copper shape that you add will be covered by soldermask except where you want the opening as defined by the real center pin.  You will get DRCs in the footprint that you can ignore; these will disappear when the footprint is dropped onto the board and the shape takes the net name of the center pin.

Hopefully this post comes through quicker than my last reply which seemed to get hung up in limbo somewhere...

Matt

I am a little late to this conversation but I just wanted to give you my feedback on how I have generated symbols like this in the past.  There are a lot of different ways of doing this and no way is better than the other but I prefer this method.

To have better control and to manage these thermal features I attempt to add them as pins so they can be easily modified to limit the amount of Static Shapes at the symbol level.  I define two Static shapes in the symbol to form the combined Top Etch and Solder Mask Pads. In addition to the 10 component pins in the device I add 8 pins, four small rectangular pins on the edges and four larger rectangular pins under the device, which define the Solder paste and drive connectivity to the thermal pad shape.  The four pins under the device have a drill in the middle, a rectangle pad on the top and round pads internal.  Finally, add one via at the center of the component in between the four larger rectangular pins.  NOTE: These additional 8 pins will require to be driven from the netlist and will be tied to a common net, most likely GND.

I attached an image that breaks down everything I said above.

Hope this helps,
Mike Catrambone
Plexus Engineering Solutions