Community PCB Design Allegro PCB Editor and PCB SKILL use pin_delay property for selected net class / match g...

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use pin_delay property for selected net class / match group

ujdaz

Hi,

I have pin_delay property assigned to the whole component (every pin of the FPGA has its own delay value assigned in the schematic library), and I am struggling with some DRCs on the PCB as for this specific design, I only need pin delay values considered for the DDR memory. If I click use pin delays in constraint manager, it calculates relative propagation delays for every signal causing DRCs for other signals, and here comes the question: is there any chance I can use pin delays in the PCB designer for specific nets / net classes without the library component modification? 

BR

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