I have a schematic that uses a REUSE module block. The symbol for the block has the typically connections that most users will be needing. However i'm making a development board for this block and wish to add test points to a couple nets inside the block which are not brought out in the symbol.
So here's what i thought to do ...
1) I added the module block with a SUBDESIGN_SUFFIX=0. Let's say the source module project has a net with SIG_NAME = "xyz". After packaging and back-annotating the physical net name (PNN) inside my schematic block is generated as "xyz_0". makes sense, no problems here.
2) I added a connector component to my main schematic and gave one of its pins a wire with SIG_NAME = "xyz_0" property in order to match the net name within the module.
3) After exporting the physical i see that the connector's net got renamed to "xyz_0_1" to differentiate it from the REUSE blocks net name that cadence deemed conflicting. that the naming was intentional and i want the net name in my schematic to be the same net within the module so i may get a rat/air-wire in the PCB.
So i understand what i going on and why it is being renamed, so my question is how to achieve the results i want without updating the module symbol? Is there a proper way to force the PNN and to let Allegro know this is intentional?
It actually seems like i can forcibly rename the pin/net in the PCB using Logic-> Net Logic , however i can't seem to back annotate or "import physical" to make it reflected in the schematic.
an update for anyone interested. My solution is to create a split symbol. Doing this allows me to make multiple symbol versions, one of which is broken out for the typical use for others. Then another symbol is made to just break out the debug nets that only i need access to. Other uses simply use just the one symbol, while i use both.