I'm trying to Place and Route hand written gate verilog, but I don't want tool to optimize logic, replace gates, etc, that's why
I place cells with the following option:
The problem is I cannot force the tool do only signal buffering optimization. In other words I want Encounter insert only buffers
without touching the gates I have used (e.g. do not replace MUX with AND-OR, etc)
Can you try limiting optDesign to only buffer insertion by disabling upsizing/downsizing/deletion with setOptMode:
setOptMode -downSizeInst false -upsizeInst false -deleteInst false
In reply to wally1:
Thanks a lot, Brian! That worked!