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P&R Optimization

Dear Friends,

I'm trying to Place and Route hand written gate verilog, but I don't want tool to optimize logic, replace gates, etc, that's why

I place cells with the following option:

placeDesign -noPrePlaceOpt

The problem is I cannot force the tool do only signal buffering optimization. In other words I want Encounter insert only buffers

without touching the gates I have used (e.g. do not replace MUX with AND-OR, etc)

Please help

Thanks,

Aram

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wally1 over 12 years ago

Hi Aram,
Can you try limiting optDesign to only buffer insertion by disabling upsizing/downsizing/deletion with setOptMode:
setOptMode -downSizeInst false -upsizeInst false -deleteInst false
Regards,
Brian
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wally1 over 12 years ago

Hi Aram,
Can you try limiting optDesign to only buffer insertion by disabling upsizing/downsizing/deletion with setOptMode:
setOptMode -downSizeInst false -upsizeInst false -deleteInst false
Regards,
Brian
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Vote Up 0 Vote Down

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