I suggest you read the "Test Point Insertion Application Note" on support.cadence.com.
In general, Random Resistant Faults are those that are difficult to test with random stimulus. Random Resistant test point insertion is used to decrease pattern count and test time.
Determinisitic Test Point insertion is used to increase coverage. It requires an ATPG experiment to be run, whereas Random Resistant analysis can be done before scan chains are inserted. Deterministic Test Point Insertion is used to achieve very high 99+% coverage in critical applications.