• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
  3. difference between Random Resistance faults and deterministic...

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 62
  • Views 15167
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

difference between Random Resistance faults and deterministic faults?

vipul982
vipul982 over 12 years ago
what is random resistance faults? how different is it from the deterministic faults? why do we do the RRFA(random resistance fault analysis)?
  • Cancel
Parents
  • bmiller
    bmiller over 12 years ago

     I suggest you read the "Test Point Insertion Application Note" on support.cadence.com.

     In general, Random Resistant Faults are those that are difficult to test with random stimulus.  Random Resistant test point insertion is used to decrease pattern count and test time.

    Determinisitic Test Point insertion is used to increase coverage.  It requires an ATPG experiment to be run, whereas Random Resistant analysis can be done before scan chains are inserted.  Deterministic Test Point Insertion is used to achieve very high 99+% coverage in critical applications.

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • bmiller
    bmiller over 12 years ago

     I suggest you read the "Test Point Insertion Application Note" on support.cadence.com.

     In general, Random Resistant Faults are those that are difficult to test with random stimulus.  Random Resistant test point insertion is used to decrease pattern count and test time.

    Determinisitic Test Point insertion is used to increase coverage.  It requires an ATPG experiment to be run, whereas Random Resistant analysis can be done before scan chains are inserted.  Deterministic Test Point Insertion is used to achieve very high 99+% coverage in critical applications.

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information