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How to use MOSFET as a switch to introduce a capacitor into a LC tank in VCO?

Alex Liao

Hi guys,

In my VCO design, if I introduce a fixed capacitance, Cap_fix into the C tank, it works fine and give me the target frequency I want. If I disconnect this path (in parallel with the total C) to disable the introduction of this Cap_fix, it gives me higher frequency and it is reasonable as it follows：
w = 1/sqrt(C*L).

But if I want to implement this on/off feature using a MOSFET it does not work.
It always generates strange frequency. I was observing the target frequency through Cadence DFT function of the output in the ADE panel.

Working as a switch, I treated the D and S ends as the switch's two ends. I biased the MOSEFT in triode (ohmic) region, which means,
give me a small Ron (1/gds) when it is on and a infinite large Ron when it is off. For MOSFET size, I tried several combinations, still not working. Either the harmonic signal's strength is high or sometimes output some unreasonable DFT waveform.

Is it such tricky on just using a triode region MOSFET as a simple on/off switch in RF circuit? Or was I implementing the switch using MOSFET in a wrong way? or any tips on bias or sizing this MOSFET? Shouldn't be the reason of my core design as it works fine by simply connecting/disconnect a regular capacitor into the LC tank.

Any reply is appreciated!
Thanks,
Alex

Parents

  • Dear Alex,

    >  if I manual introduce some Resistance for the inductors and some
    > paracitics (maybe anywhere in the circuit), the output swing should
    > be decreased. Is that right?

    Yes. I believe the added parasitic elements will reduce the magnitude of the sustaining amplifier's negative resistance and hence the steady-state oscillation amplitude relative to the amplitude you are now observing.

    >  Is there any specific nodes, once parasitics appear, that make the
    > performance very parasitic sensitive?


    I think you will gain more insight if you experiment with the location and sensitivities of added parasitics than if I suggest specific nodes and circuit traces. Hopefully, you will agree.

    >  I am presenting the adopted equations I tried in the output setup
    > or in the ADE calculator. None of them work.

    I can only guess what "net1" and "net2" are - and perhaps /I0/M1/G is the gate current of the MOS switch? I am not sure what impedances you are trying to measure. Perhaps the expressions are not working if you have not saved the gate current and hence it returns "nil"?

    In my first response, i added that it might be best to use a separate test circuit to study the small and large signal impedances of your MOS switch. In the test bench, I would bias the MOS device as it will be biased in the VCO. You can use an ideal inductor of large value to make the impedance to any DC source you use for biasing very large relative to the impedance you are trying to measure. Apply an ideal current source to the node(s) that you want to measure the impedance and then perform a large or small signal sinusoidal analysis. The resulting impedance can be measured by taking the ratio of the voltage waveform  across the current source divided by the waveform of the applied current. The ratio will be a function of frequency and will have real and complex parts. Hence, you can study the real and imaginary equivalent impedances at any specific frequency using the value() function for a specific frequency of interest. For a small signal analysis, you can set the amplitude of the current source to 1 with 0 phase and the resulting voltage will have the units of ohms. You will not need to take the ratio.

    I hope this helps Alex. Perhaps Andrew sees a syntax error with your expressions that I overlooked. He is far more skilled at quickly catching syntax errors than I!

    Shawn

Reply

  • Dear Alex,

    >  if I manual introduce some Resistance for the inductors and some
    > paracitics (maybe anywhere in the circuit), the output swing should
    > be decreased. Is that right?

    Yes. I believe the added parasitic elements will reduce the magnitude of the sustaining amplifier's negative resistance and hence the steady-state oscillation amplitude relative to the amplitude you are now observing.

    >  Is there any specific nodes, once parasitics appear, that make the
    > performance very parasitic sensitive?


    I think you will gain more insight if you experiment with the location and sensitivities of added parasitics than if I suggest specific nodes and circuit traces. Hopefully, you will agree.

    >  I am presenting the adopted equations I tried in the output setup
    > or in the ADE calculator. None of them work.

    I can only guess what "net1" and "net2" are - and perhaps /I0/M1/G is the gate current of the MOS switch? I am not sure what impedances you are trying to measure. Perhaps the expressions are not working if you have not saved the gate current and hence it returns "nil"?

    In my first response, i added that it might be best to use a separate test circuit to study the small and large signal impedances of your MOS switch. In the test bench, I would bias the MOS device as it will be biased in the VCO. You can use an ideal inductor of large value to make the impedance to any DC source you use for biasing very large relative to the impedance you are trying to measure. Apply an ideal current source to the node(s) that you want to measure the impedance and then perform a large or small signal sinusoidal analysis. The resulting impedance can be measured by taking the ratio of the voltage waveform  across the current source divided by the waveform of the applied current. The ratio will be a function of frequency and will have real and complex parts. Hence, you can study the real and imaginary equivalent impedances at any specific frequency using the value() function for a specific frequency of interest. For a small signal analysis, you can set the amplitude of the current source to 1 with 0 phase and the resulting voltage will have the units of ohms. You will not need to take the ratio.

    I hope this helps Alex. Perhaps Andrew sees a syntax error with your expressions that I overlooked. He is far more skilled at quickly catching syntax errors than I!

    Shawn

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