i´m working on several versions of my chip-core in parallel and i want to reduce the effort to change the powergrid everytime i test my layout.
To make it behave like there would be a powergrid on top i just want to copy a VDD/VSS label on the pinlayer of the corebar every 10 um.
So my question is :-):
Does the PLS-extractor connect every pin-label with the belonging net or does it delete all except one and then connects the net to it?
Thank you for your help,
What tool is the PLS extractor? I would assume, based on most extractors, if the names all agree and the wires are all physically connected, it would assign it correctly. If the names were different on a physically connected net, it would give an error. If the nets were not physically connected, the extractor would need to understand that the labels are for a global net, this is tool dependent (: for dracula, ! for diva/assura, declared global for some other tools).
In reply to Austin CAD Guy:
we use Synopsys Star-RCXT for the extraction.
It seems that from a certain amount of pins the extractor doesn´t consider all off them. I´ve got a timeinterleaved structure with two equal parts. Extraction of just the single circuit and simulation in an upper schematic as the timeinterleaved structure delivers good results.
If I design the whole structure and simulate the extraction result with nearly two times the amount of pins it delivers signals outside saturation region (in time domain only for the second part of the structure) and FlipFlops which don´t switch due to power supply reasons. There are about 1500 VDD and VSS pins, so maybe there is some kind of upper boundary? :-) I´ve tried the same structure with a power grid on top and only few powerpins (about 8 each) and it works...