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Behavior of multiple label-pins while extraction

flang

 Hi,

i´m working on several versions of my chip-core in parallel and i want to reduce the effort to change the powergrid everytime i test my layout.

To make it behave like there would be a powergrid on top i just want to copy a VDD/VSS label on the pinlayer of the corebar every 10 um.

So my question is :-):

Does the PLS-extractor connect every pin-label with the belonging net or does it delete all except one and then connects the net to it?

 

Thank you for your help,

Felix

Parents

  •  Hi Felix

     What tool is the PLS extractor? I would assume, based on most extractors, if the names all agree and the wires are all physically connected,  it would assign it correctly. If the names were different on a physically connected net, it would give an error. If the nets were not physically connected, the extractor would need to understand that the labels are for a global net, this is tool dependent (: for dracula, ! for diva/assura, declared global for some other tools). 

     Ted

Reply

  •  Hi Felix

     What tool is the PLS extractor? I would assume, based on most extractors, if the names all agree and the wires are all physically connected,  it would assign it correctly. If the names were different on a physically connected net, it would give an error. If the nets were not physically connected, the extractor would need to understand that the labels are for a global net, this is tool dependent (: for dracula, ! for diva/assura, declared global for some other tools). 

     Ted

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