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dbGet
Encounter Digital Implementation
puzzler
tcl

Encounter Puzzler #3: Renaming a Net Logically

28 Feb 2011 • 1 minute read

The other day a designer E-mailed me: How can we rename a net in Encounter?

I followed up to clarify whether the designer wanted to change the net associated with routed wire segments, or wanted to rename a signal net. He clarified that he wanted to change a logical signal net's name.

Changing the net name associated with a routed wire segments is described in this solution:

editSelect -nets VDD1
editSelectVia -nets VDD1
editChangeNet -to VDD2

However, it's not so easy to change a logical net name in Encounter. The "name" field for a net isn't editable in the Attribute Editor, there is no "dbSetNetName" command, and dbGet says the "name" attribute of the "net" object type isn't settable:

encounter 1> dbGet top.nets.?h
name: string, Canonical (flat) name of the net

If an attribute is settable dbGet will say "settable" after the attribute name. For example:

skipRouting(settable): bool, Specifies that Nanoroute should not route or re-route the net.

So how can we change the net name programatically? How would we take this netlist:

module testcase ();
 wire net;
 BUFX1 i0(.Y(net));
 BUFX1 i1(.A(net));
endmodule

...and turn it into this:

module testcase ();
   wire new_net;
   BUFX1 i0 (.Y(new_net));
   BUFX1 i1 (.A(new_net));
endmodule

Today's puzzler is to write a TCL script called "userChangeNetName" that changes the logical net name of nets programmatically:

proc userChangeNetName {oldNetName newNetName} {
  <your solution here>
}

Leave your solution as a comment below. I'll post further discussion and a round-up on Friday.

We're looking to change the net name logically so don't worry about things like wire segments or physical I/O pins.

For extra credit, check whether your scripted solution can handle the case where the net is connected to an I/O port and/or connected through Verilog hierarchy like top-level net "in" and "net2" in this example:

module testcase (in);
 input in;
 wire net1, net2;
 BUFX1 i0(.Y(net1));
 BUFX1 i1(.A(net1));
 BUFX1 i2(.A(in));
 BUFX1 i3(.Y(net2));
 a i_a(.in(net2));
endmodule

module a(in);
 input in;
 BUFX1 i0(.A(in));
endmodule

Related Reading:

  • Encounter Puzzler #1: Where did my fences go? 
  • Encounter Puzzler #2: Finding registers beneath a hierarchy

I'll look forward to seeing your solutions!

Update: Click here to see solutions and discussion about this puzzler

Bob Dwyer


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