Report From DesignCon 2009

This week the "DesignCon" show is in town (<= 10 minutes from the Cadence campus at the Santa Clara convention center), so I couldn't resist the opportunity to check out some of the speeches and exhibits.  I'm happy to report that my curiosity was rewarded -- here are my notes along with some photos:

* First, full disclosure: Cadence -- both Corporate and Chip Estimate -- have modest 10x10 booths on the show floor.  Even better (from my biased POV): the verification group has one of the demo pods:

Mirit from Verification R&D goes into specific detail on our planning & management capabilities

That said: I know what some of you in the verification space are thinking: isn't DVCon more of the type of show where the Verification Group would be exhibiting?  The answer is "yes" and "yes": yes we will be at DVCon in a few weeks;and "yes", we in the Verification Group normally do not support DesignCon.  However, long story short, a demo pod in the booth became available and we seized the opportunity to exhibit.  Based on unscientific observations of the quantity and quality of the prospects Tom and Mirit were talking with, things seem to be panning out.

Bottom-line: If you are in the Silicon Valley area and decide to check out the free exhibits on Wednesday 2/4, please stop by to discuss your verification challenges (and while you are there, enter to win a Wii game console).  Regardless of whether or not you get this opportunity to touch base with us at DesignCon, I strongly urge you to mark your calendar for DVCon from February 24-26 here in Silicon Valley as we will be there in force.

* In a spot of good news for the electronics industry and the economy in general, my unscientific impression was that the show floor traffic was at a "reasonably healthy" level.  Vendors in booths both big & small were engaging with a good number of customers & prospects, and the Cadence booth was drawing its share of traffic (vs. some past trade shows where the aisles are empty, and booth crews are chatting with each other)

* Last but not least: my colleagues at Chip Estimate won the "Design Vision" award for Semiconductor IP for the ChipEstimate.com IP Ecosystem.  Congratulations!

Members of the ChipEstimate Team accepting the "Design Vision" award for Semiconductor IP