An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog

In my last blog entry, I implored Accellera to release UVM 1.0 quickly, standardizing OVM 2.1 as is, with full backwards compatibility and without trying to cram overlapping functionaity from VMM into the base. Then they can add new functionality on top of this base, taking good ideas from OVM World Contributions, VMM, in-house methodologies developed by the member companies, etc.

It occurs to me that Accellera faced a similar situation during the early days of SystemVerilog.They chose Verilog-2001 as the base for SystemVerilog, maintained backward compatibility, and did not try to stuff overlapping VHDL constructs into the base. Then they added lots of new functionality on top of the base, taking good ideas from VHDL, Superlog, Vera, e, C/C++/SystemC, etc.

Just imagine what would have happened if Accellera had mashed Verilog and VHDL constructs together into the SystemVerilog base, or even worse if they actually changed some of the syntax so that SystemVerilog was not backwards compatible with Verilog. The resulting language would have been a mess, and countless thousands of Verilog users would have had to recode.

I sincerely hope that there are no thoughts within Accellera of mashing VMM features into the UVM's OVM base or of doing anything to break OVM backwards compatibility. Accellera must ensure that UVM 1.0 = OVM 2.1 and then put its energy into enhancements for future UVM releases. Anything else would be a nightmare for the countless thousands of OVM users.

Tom A.

The truth is out there...sometimes it's in a blog.