"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra.  All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models.  The good news for them and the rest of the community is that Cadence is driving these features and more in the Accellera VIP TSC and delivering Incisive Enterprise Solutions to run effective UVM-based verification within 2010.

True to my @SeeAdamRun Twitter avatar, I believe the best way for a marketing guy to know what the users need is to actually go and visit them.  During the past week, I visited customers throughout Europe providing a Cadence view of the UVM 1.0 development status in the context of the Incisive Enterprise Solution.  Of course, visiting happy-as-a-clam Cadence OVM users is fait accompli with respect to the UVM migration and that's not enough fun.  One needs to visit customers who could be, or in fact are, on the fence to understand their needs.  Given that, here's a few stats on the customers we saw.  (Sorry competitors, no names!)

• 8 OVM SystemVerilog users including 3 mixing OVM e with SystemVerilog and one Vera-->OVM migration
• 2 VMM users including one VMM 1.2 and one VMM-->OVM migration
• 2 custom SystemVerilog library users

In each customer visit we presented a short refresh on the history of the UVM development and a preliminary look at the technology being developed for UVM 1.0.  Of the big three items -- phasing, register package, and TLM2 subset -- the register package was of course the hottest topic.  The register package provides a connection from the register descriptions, typically captured in IP-XACT using tools from companies like Duolog, to the verification environment for control, randomization, coverage, and more.  Customers were happy to hear that Cadence is working within the TSC to review and improve the new register package being developed as part of UVM 1.0.

Phasing enables multiple UVM Verification Components (UVCs) to more easily control the aspects of reset, configuration, execution, and shutdown that consume time during simulation, as well as more easily integrate those steps when they are brought together into a verification environment.  It was really clear to each team how the phasing is defined and most expect to apply it in their environments.  The TLM2 standard adds features to improve the communication with SystemC and the modeling of busses in the testbench. The plans for TLM2 were squarely aligned with one of the users, and several others understood the value, but most did not plan to use that technology initially.

Once we discussed the UVM 1.0 plan, the next question was when will Cadence support it?  That's an easy one.  We've had full support in our simulator since the summer for UVM 1.0 EA and we're adding verification IP support this fall.  Our engineers are running all of the UVM 1.0 code in the Accellera development areas with our existing simulator releases, so we anticipate no issues with the UVM 1.0 when it is available later this year.  The OVM e (eRM) users also asked about interoperability. We reminded them of the OVM multi-language solution we provided to the industry almost 2 years ago and that we are updating that to UVM. Another question was about checking for UVM compliance. Here we pointed to the tools provided by Amiq using rule decks provided by Cadence.  That's EDA360 at work, my friends.

So then we came to the final question -- when do you want it?  Each SystemVerilog user said that they want UVM 1.0 now.  With the information we provided, they all said that they are making plans now to move to UVM 1.0 in early 2011.  The OVM users are doing their test migrations using the OVM to UVM script we wrote for Accellera in Q4 to be better prepared, and the VMM users are making plans as well.

So, when are you moving to UVM 1.0?

Adam Sherilog, Incisive Product Management Director