• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Verification
  3. Does It Get Any Better than CDNLive! India?
tomacadence
tomacadence

Community Member

Blog Activity
Options
  • Subscribe by email
  • More
  • Cancel
CDNLive
formal
OVM
ISX
MDV
IFV
techtorial
India
verification

Does It Get Any Better than CDNLive! India?

18 Nov 2010 • 3 minute read

I've just returned from CDNLive! India in Bangalore, fired up with the huge crowd, their avid interest in Cadence and our products, and both the quantity and the quality of the user sessions. Of course I was impressed with CDNLive! here in Silicon Valley too; I blogged about that a couple of weeks ago. But the India show has at least as many attendees, plus there was something extra in their level of enthusiasm. Even after the sessions, entertainment, beverages and dinner were over, I still saw users and Cadence employees chatting in groups all around.

Another measure of the show's success is the intense competition for user presentations. More than 140 abstracts were submitted, of which less than one-third were accepted and presented. Judging by the high quality of the talks I saw, surely some of those abstracts not selected were also worthy. We always wish that we could present more sessions from all of you smart users out there, but inevitably there are venue limitations. In addition, too many parallel tracks can make it hard for attendees to decide which talks to see.

I faced that dilemma myself at this event, since I presented both a verification update in the Silicon Realization: Verification and FED track, and an overview of System and SoC Realization in the corresponding track. There were interesting verification-related user talks in both, so I ended up switching back and forth between the two tracks all day. I jotted down notes on several of these talks, so I'll take advantage of this post to share some of what I heard and some of my observations.

As is always the case at CDNLive! India, Incisive Formal Verifier (IFV) was well represented, this time with three solid technical talks. Texas Instruments discussed their use of IFV for verifying design-for-test (DFT) logic, a project so successful that they eliminated 90% of their reliance on simulation for this verification task. Freescale gave some concrete examples of design corner cases, many related to low-power operation, which were thoroughly verified with IFV. Both of these were the sort of specific, user-to-user talks that work best at these shows.

The third talk, from Nokia, summarized how they used IFV for several different formal applications in the verification of a wireless modem design. I found this session especially interesting and worth of follow-up, so I'll reserve the details for a separate blog post.

A talk by STMicroelectronics included my favorite quote of the whole show - "e was an obvious choice for us" in reference to the team's expertise, the power of the language, and the availability of high-quality verification IP (VIP). They described how they create an e-based metric-driven verification (MDV) environment that starts with abstract transaction-level modeling (TLM) of their network-on-chip design. They are able to reuse the same environment at multiple abstraction levels, including RTL, leveraging a vitally important dimension of scalability.

Texas Instruments also showed the power of the e language by focusing on another dimension of scalability: moving from IP verification to full-chip SoC verification. They build an IP-level testbench using Cadence's e implementation of the Open Verification Methodology (OVM) library, and then are able to scale up to the complete multi-language SoC verification environment. They described their approach as "the way forward for verification strategy and methodology of complex IPs and SoCs."

Other verification sessions of interest included the use of Palladium XP for power prediction, combined hardware-software MDV using Cadence Incisive Software Extension (ISX), development of TLM-based verification IP, and verification of SystemC TLM designs. I couldn't attend all of these talks, so in the interest of keeping a crisp blog post I'll direct you to the program for more details.

As you can tell, I had a great time at CDNLive! India, followed by a couple of productive days with our verification R&D teams in Noida. I don't make it to India as often as I would like but I always enjoy myself and marvel at how tremendously the country has changed just in the fifteen years since my first visit. I've already given my management a head's-up that I'll be at the front of the queue asking to return to the big show next year. I hope to see some of you there!

Tom A.

The truth is out there...sometimes it's in a blog.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information