At DVCon 2011 Next Week

Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics.  If you are within a tank of gas or a Southwest flight of San Jose, going to DVCon is a no brainer.  I guarantee that you WILL learn something -- whether it's from the aforementioned events, or just chatting with other attendees who are struggling with verification challenges similar to yours.

Still on the fence?  Need something to prove to your boss this conference is no boondoggle?  Here are some images and articles from past DVCons to give you a flavor of the proceedings, and the high caliber of engineers you will meet there:

DVCon "Day 0" - Quick Report From SystemC Day

Annotated photo galleries of DVCon 2010 Day 1, Day 2, Day 3

Video interview of Cadence R&D Architect and language guru Matan Vax on his DVCon 2010 paper "Where OOP Falls Short of Hardware Verification Needs"

Select posts on DVCon 2010 from Richard Goering's Industry Insights blog:

Challenging Misconceptions About Verification Languages

DVCon Panel: Three Ways To Minimize Verification Effort

DVCon OVM Panelists: Easing The Debug Challenge

DVCon Panel: Why Verification Engineers Are "Sleepless"

DVCon SystemC Day - Forging A TLM Design/Verification Flow

DVCon SystemC Day Quandary: Need for Third Party TLM IP

UVM-MS - Metric-Driven Verification for Analog IP and Mixed-Signal SoCs

More details about this year's show:
Cadence will offer demos, deliver papers and participate on panels throughout the four-day show.  Our methodology and R&D will be available at Booth #1005 to discuss the latest technologies and methodologies supporting the EDA360 vision, as well as the following events:

• The Feb. 28 "SystemC day" with the North American SystemC User Group (NASCUG), 8am-12pm
• The Feb. 28 "UVM Workshop," held 9 a.m. to 5 p.m. in the Pine/Cedar Ballroom
• A March 1 panel discussion titled, "UVM -- Final Answer or Phone a Friend?" from 2 p.m. to 3:30 p.m. in the Oak/Fir Ballroom
• A March 3 Cadence-sponsored tutorial, from 8:30 a.m. to noon in the Siskiyou Ballroom, titled, "Good Fences Don't Make Good Neighbors: A Comprehensive SoC and System Verification and Validation Tutorial"
• A March 3 luncheon panel, at noon in the Donner Ballroom, titled, "Mixed Signal is No Longer The Other Guy's Problem"

Technical sessions with Cadence-contributed content include:

Tuesday March 1

• Session 2.4: Mixed-Signal Approaches in Assertion-based Verification: New Frontiers
• Session 3.4: UVM-MS: Metrics-driven Verification of Mixed Signal Designs
• Session 5.2: Transaction Based Acceleration -- Strong Ammunition in Any Verification Arsenal
• Poster Session 2P.2: Case Study: Power-aware IP and Mixed Signal Verification
• Poster Session 2P.3: Case Study: Low-power Verification Success Depends on Positive Pessimism

Wednesday March 2

• Session 7.3: Optimizing Area and Power Using Formal Methods
• Session 11.3: An Automatic Visual System Performance Stress Test for TLM Designs

Additional details are available at the DVCon 2011 web site.

Last but not least: when you hit the expo floor, be sure to get out your "EDA360 Passport" for a chance to win a Flip UltraHD Video Camera ...

See you next week!

Joe Hupcey III

On Twitter: http://twitter.com/jhupcey, @jhupcey