Innovative Approach to Optimized FPGA Pin Assignment

Cadence has been a leader in silicon-package and package-board co-design for over a decade now. Today, Cadence introduced a new and innovative solution for FPGA-PCB Co-design.

The FPGA-PCB co-design solution includes proven technology from Taray Inc for optimized, correct-by-construction FPGA I/O pin assignment synthesis that takes into account the placement and routing of the FPGAs.

What is unique about this technology is:

• It provides automated FPGA I/O pin assignment that is accurate per FPGA vendors' pin assignment guidelines
• It enables architecural exploration to do cost/performance trade-offs that is not practical with manual pin assignment methods.

To learn more about this exciting new approach, read more:

• Cadence Introduces Innovative FPGA-PCB Co-Design Solution - Cadence Article
• Allegro FPGA System Planner - Product information / Datasheet
• Cadence OrCaD FPGA System Planner - Product information / Datasheet
• Successfully designing FPGA-Based Systems - white paper
• Cadence Introduces Innovative FPGA-PCB Co-Design Solutions -press release

Hemant Shah