Renesas Collaborates on Large Language Model Generative AI Chip Design

Renesas and Cadence have been collaborating for several years, combining their expertise to drive advancements in chip design. Their partnership has been instrumental in creating innovative solutions that address the complex challenges faced by chip designers in today's rapidly evolving technological landscape. Most recently, the collaboration has focused on generative AI and its impact on semiconductor quality and design team productivity. They are also early adopters of Cadence Generative AI solutions, including Cadence Cerebrus for chip implementation, Verisium AI-driven verification, and the Cadence Joint Data and AI (JedAI) Platform.

The world of generative AI is evolving rapidly! I'm now a regular user of ChatGPT for various projects at work and home. At Cadence, we are seeing a dramatic uptick in adopting our JedAI generative AI solution. We recently announced the industry's first large language model (LLM) for chip design (a proof of concept project named ChipGPT) and the OrCAD X Platform for PCB design, optimized for small and medium businesses.

The collaboration with Renesas has continued with ChipGPT. The project set out to validate that the proof of concept would be impactful. The questions we sought to answer included: Can LLMs increase the quality of the code created by engineers, drive alignment between semiconductor designers and teams, reduce the frequency of engineering meetings, lower overall design costs, and speed time to market?

The results of a groundbreaking LLM pilot project revealed that the answer to the above question is "yes." AI can dramatically shorten the chip design process, speed products to market, and potentially lower design and manufacturing costs by millions of dollars.

"Ensuring alignment between specification and design is critical, and the cost of verification has increased with the complexity of design functions. Renesas and Cadence have collaborated to develop a novel approach to address this challenge by leveraging generative AI's LLM capabilities, which significantly reduce the time from specification to final design by efficiently controlling design quality. This remarkable milestone is an achievement in the long-term collaboration between Renesas and Cadence to develop advanced AI technology that revolutionizes semiconductor design processes and accelerates time-to-market."

Shinichi Yoshioka
Senior Vice President and CTO, Renesas

Forbes interviewed Mr Yoshioka, who answered many detailed questions about the proof of concept.

The strategic collaboration between Renesas and Cadence has been a driving force in the semiconductor industry, particularly in AI technologies. Developing a significant language model capability tailored for chip design has revolutionized how designers approach their work, enabling enhanced design exploration, reduced time-to-market, improved chip performance, and increased collaboration. As Renesas and Cadence continue to push the boundaries of innovation, the future of chip design looks promising, driven by the power of AI technologies.