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With the surge in usage requirements and increasing customer demands, hardware design is quickly becoming more complex. The rapid change in market trends, with a greater focus on technologies such as electric vehicles, dictates the demand for efficient power management and high-performance processing. Verification throughput continues to be a bottleneck as SoC designs increase in size, and so do the complexities. Adding more CPU cores and running more tests in parallel does not scale sufficiently. All this adds to the strain on verification engineers in verifying such complex designs.
Verification is never complete; it is over when you run out of time. The goal is to make the verification process converge before you run out of time. Everyone wants to see key metrics converge to target goals and do so within stringent cost and time constraints. Imagine sitting in a cockpit, feeding inputs to the blackbox, and waiting for the magic to happen (press a button, and your job is done). The need of the hour is how artificial intelligence and machine learning (AI/ML) can help us get our regression faster, help save debug time, meet our verification/coverage goals, and manage resources and money—in other words, how can we use AI/ML to increase efficiency in verification?
Renesas, a pioneer in semiconductor design, was facing similar challenges. Market pressure and strict tapeout schedules pushed them to look for a technology/methodology to optimize simulation regressions and accelerate the design verification process throughout product development. They wanted to reduce the risks, find as many bugs as possible early, be able to debug fast, and meet the demands of their end users.
Renesas started exploring the Cadence Xcelium Machine Learning App. This app uses machine learning technology and optimizes simulation regressions to produce a well-condensed regression. This optimized regression was then used to reproduce almost the same coverage as the original regression and to find the design bugs quickly by simulating the corner case scenarios possible with the existing randomized testbench.
Renesas achieved excellent results and saved 66% of their complete random verification regression cycle. This was a considerable saving of resources, cost, and time. The Xcelium ML App helped them achieve 2.2X compression with 100% coverage score regain. Furthermore, when using the ML regression on the first derivative, Renesas achieved a 3.6X reduction with 100% coverage score regain.
The ML regression runs (1168) = 1/3 original regression runs (3774). This helped them get ahead of the curve 30% faster and meet the time-to-market demands.
In addition to saving resources and time and accelerating coverage closure with the Xcelium ML App, they evaluated Cadence’s Verisium AI-Driven Verification Platform, including three Verisium Apps, boosting up to 6X in verification productivity. Renesas was able to save ~ 27 work hours.
Renesas evaluated the following apps:
Together, Cadence’s Verisium Platform and Xcelium ML App provide a suite of applications leveraging AI/ML to optimize verification workloads, boost coverage, and accelerate root cause analysis of design bugs on complex SoCs. Renesas leveraged the AI platform and increased their verification productivity by up to 10X.