Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence reported on what it took to pull together a version of Innovus Implementation System and a version of the ARM physical library that would work cleanly at 10nm. They titled their talk Routing at 10nm, Challenging but Achievable With Collaboration. There are a lot of moving parts in a design like this, with EDA tools from Cadence, standard cells from ARM, the foundry. That is before adding in other IP, and let's not forget about the system/SoC company actually doing the design.
So what's new at 10nm? There is, of course, the usual fact that designs get larger, which stresses the tools more, especially since computers don't keep getting significantly faster every couple of years to bail us out. So what are the other changes at 10nm?
These changes, in turn, translate into requirements (aka challenges) for the EDA tools, primarily Innovus Implementation System, and for the standard cell provider (ARM, in this case).
For Innovus Implementation System, one big challenge is that design rules don't always map from the DRM (design rule manual) to the LEF for the routing world. Indeed, to support some of them, there are additions to the LEF syntax. Plus, code needs to be written to handle the new placement requirements and the automatic generation (autogen) of vias in the color-aware environment. Of course, that means, inevitably, working with early versions of the code, buggy versions of the code, and living with limitations until the code can handle them.
Meanwhile, on the physical library side there are challenges. The first is to interpret the complex DRM and turn that into a standard cell architecture. Then, those cells need to be passed through unstable versions of Innovus Implementation System as the code just described is being written concurrently. Ultimately, a standard cell library is only as good as the results after place and route.
There are a couple of new LEF constructs. It is a level of detail too far to describe them fully here, but the keywords are WITHINFIRSTWIDTH (which are rules for via enclosure) and THREECONCAVECORNERS (which are rules for specific situations to improve DFM).
The whole handling of vias is different at 10nm. Some via structures are described in the LEF explicitly, and some are autogenerated. On top of that, for clock and power, due to the high currents, there are NDR (non-default rule) via structures.
The end result:
Of course, neither ARM nor Cadence actually builds SoCs (except for the Palladium emulation platform, in Cadence's case). The result of all this work means that there is a library and a flow for customers to do 10nm designs.
Next: Andrew Kahng on Industry-Academia Cooperation
Previous: What Is RocketSim? Why Did Cadence Acquires Rocketick?