RISC-V Gathering Momentum

I've been writing quite a bit about RISC-V (pronounced "risk five") since I think that it is going to turn out to be very significant, although it is still early days. However, momentum is truly building behind the instruction set architecture (ISA). A week or so ago I talked to Krste Asanović, who is the UC Berkeley professor who led the project to define RISC-V, chairman of the RISC-V foundation, and in July co-founded a fabless semiconductor company, SiFive, to produce silicon implementations (and IP). I'll talk about SiFive in Breakfast Bytes one day next week.

RISC-V has taken off strongly in academic circles due to its unrestricted availability compared to other instruction sets, which are often not really ideal for academic work, and/or come with legal encumbrance. But strong growth in academia is nothing compared to strong growth in industry. Look at something like Pascal versus C in the software world.

In July, there was the latest RISC-V workshop at MIT in Cambridge, MA (I mentioned that I studied CS at the "real" Cambridge and it turned out Krste did, too, Well he technically studied EIST, the Electrical and Information Sciences Tripos. So that's how he has an English accent). Earlier this year at the January workshop, there were 16 member companies for the RISC-V Foundation. Now there are 41 founding members. There is a long line of other companies joining and Krste reckons that by the next RISC-V workshop there could be twice as many as the current 41. These are not insignificant companies, either. Founding members include Google, Microsoft, Oracle, Qualcomm, AMD, IBM, HP Enterprise, NVIDIA, Mellanox, Microsemi, Rambus, Western Digital, Lattice, and more.

Probably some of these companies are passive observers, taking a wait-an-see approach. But real things are happening. Here are some significant recent announcements to give you a sense of how much things are snowballing:

Google has a bootstrap called coreboot. When an engineer makes changes to it, if it breaks RISC-V then the changes cannot commit. This is not just being a passive observer, although nobody knows just what Google are doing.

HP Enterprise ported UEFI, the unified extensible firmware interface to RISC-V. This is "big ball of mud" code with a huge amount of history, so non-trivial to port. Certainly not something you would do for fun. UEFI is the replacement for the original BIOS in all PCs, but it is not just used for x86. ARM uses it for server systems, too, for example.

At the July workshop, Joe Xie of NVIDIA explains why all future NVIDIA products will contain a RISC-V control processor, eventually completely replacing the proprietary ISA FALCON (FAst Logic CONtroller) which was introduced 10 years ago and has been on at least 15 different NVIDIA produts. Watch the video:

India has selected RISC-V as the national ISA since they want to be able to be self sufficient, and are apparently investing $45M in the development of a 64-bit implementation.

Andes (a processor IP company based in Hsinchu, Taiwan) have been reasonably successful with their own ISA (there are over 10,000 installations of their software development environment installed). They have joined RISC-V Foundation so it would be a good guess that they plan to produce cores using the RISC-V architecture.

Cortus (a processor IP company based in Montepelier, France) has joined RISC-V although they have not (yet?) announced any RISC-V cores..

Codasip (a processor IP company based in Brno, Czech Republic) has already announced it is making available versions of its Codix Processor IP that are compliant with the RISC-V specification.

Andrew Canis of LegUp discussed Lattice Semiconductor's RISC-V processor that can be programmed into their FPGAs, and their own custom accelerators. Watch the video:

CEA Tech (a research organization based in Grenoble, France) has developed an FD-SOI RISC-V core, presumably in co-operation with ST Microelectronics.

Plus SiFive, founded by the team that developed RISC-V and backed by Sutter-Hill Ventures. More about that next week.

One dynamic that will be interesting to watch will be the Softbank acquisition of ARM (not yet complete, of course). If Softbank competes too aggressively with existing licensees, then RISC-V is the obvious alternative if anyone feels they need to jump ship. Since Softbank is a Japanese company, and there is a general distrust between China and Japan, the issue is probably most acute in China.

Krste told me that companies often start off saying "It's a free ISA." Now they are at the phase of saying "It's a good ISA." As he said at DAC, "Our modest goal is to become the industry standard for all computing devices." It's certainly moving in that direction.

By the way, you can now watch the video of Krste's presentation at DAC that I covered in RISC-V: Instruction Sets Want to be Free:

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