5nm: Do You Take the Red Pill or the Blue Pill?

I wrote recently about the TSMC OIP Symposium where they talked about future devices: Ge FinFET, III-V FinFet, III-V GAA FET, stacked GAA nanowire FET, tunnel FET, graphene nano ribbon, and carbon nanotube. Why all these weird materials?

If you go to any presentations on future process technologies at places like imec, IEDM, or SEMICON West, you will hear about a fundamental limit of silicon, which is that the subthreshold slope for silicon is 60mV/decade. What does this mean? The threshold voltage V_th has to be about 1/3 of the power supply voltage, V_dd, for normal digital circuits. So if V_dd is 0.9V, then V_th is 0.3V, or 300mV. At 60 mV/decade that means 5 decades (300 / 60) or 100,000.

That means that the ratio between the ON current and the OFF current is 5 decades or 100,000. If, as we usually do, we want high drive current, then that means the OFF current will be high, too, meaning high leakage. This is a fundamental property of the material (silicon), which can only be escaped by either using a different material or something other than an MOS transistor. Otherwise you can't get lower than 60mV/decade.

For example, carbon nanotube transistors have 40mV/decade. Or TFETs (tunnel field effect transistors) have about 3X higher drive strengths and a SS of around 33mV/decade. To learn more, look at my post from SEMICON in Pathfinding Beyond 5nm, or my post from imec on An Stteegen's Secrets of Semiconductor Scaling. Or IEDM Examines Options for 5nm.

One of the most famous lines from The Matrix is:

You take the blue pill, the story ends. You wake up in your bed and believe whatever you want to believe. You take the red pill, you stay in Wonderland, and I show you how deep the rabbit hole goes.

At IEDM last December, Mark Lundstrum split the solutions into a similar choice. The red solution is to live with the 60mV/decade, but find a way to increase the ON current so that we can get back to the same drive at a lower voltage, and thus lower leakage, too. The alternative is to use something other than silicon MOS transistors. He called these the red option and the blue option.

For 5nm, it's not that simple though. The two approaches are illustrated on the graph below. The red option has subthreshold slope (SS) at 60mV/decade or above. The blue option has a lower SS due to a completely different transistor architecture or a different material. But the big challenge, apart from manufacturing cost and feasibility for some approaches, is the difficulty of achieving the desired ON current at a voltage that doesn't give you an undesirable OFF current.

Because, at 5nm, predictions are for a power supply voltage of 0.5V. That means a threshold voltage V_th of around 0.17V, so at 60 mV/decade that means 2.8 decades, so the ratio of the ON current to the OFF current will be less than 1000. So leakage will be totally unacceptable without re-engineering the transistor.

That's why nobody can really tell you what 5nm is going to be like.

Further, that is before considering whether 5nm will be economically feasible or whether it will only be affordable to a handful of customers, making it hard to recover the cost of technology development and constructing a fab. "7nm is for seven customers, 5nm is for five customers" as Riko Radojcic joked at EDPS, his previous employer Qualcomm presumably being one of them. It might be too true.

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