RISCy Business: Next Hogan Evening at ESD Alliance Is RISC-V

11 Jan 2017 • 2 minute read

The ESD Alliance Emerging Companies have been organizing a series of evening events, sometimes panel sessions, sometimes interviews. The thread tying them all together is that they are hosted by Jim Hogan (who is an independent investor these days, although he spent many years in a variety of different positions at Cadence, and even SDA before Cadence existed). The latest in the Jim Hogan Series will take place next week on January 18 from 6:00pm to 8.30pm. It will actually be held, not at the ESD Alliance facilities like in the past, but at Cadence. It doesn't give details of exactly where but I'm assuming it will be in the building 10 auditorium.

The topic is Open Source Processors and the RISC-V Project. This is something that I've been following closely since I first heard about it at the start of this year. I immediately felt that it was important and have been tracking it since, most recently attending the RISC-V workshop held at the end of November at Google.

The very brief history of RISC-V (which is pronounced risk-five) if you know nothing about it, is that it was created by a team at UC Berkeley led by Krste Asańovic since they needed an instruction set architecture (ISA) for teaching, and the obvious choices of ARM and Intel (technically AMD) x86 were too complex and too legally encumbered to be practical. There turned out to be a pent-up demand and soon other universities started to use it. Industry has gradually taken notice and when the RISC-V Foundation was created, founder members included such companies as Google, HP Enterprise, NVIDIA, IBM, Qualcomm, Oracle and many more. NVIDIA needed a new control processor for their GPUs, and they stated at the fourth workshop that all future GPUs would contain a RISC-V ISA control processor. Google will not allow developers to commit their server bootstrap if RISC-V is broken. HP created a RISC-V version of UEFI (the modern BIOS).

The developers of the RISC-V ISA created a company, SiFive, to commercialize silicon implementations and announced at the recent fifth workshop that the first silicon was back from the fab and working. They also open-sourced the entire hardware design (which is done in a high-level language called Chisel, which generates the RTL as an intermediate form).

The two panelists at the evening will be:

Rick O'Connor, Executive Director of the RISC-V Foundation
Yunsup Lee, one of the original developers of the ISA at Cal, and now CTO of SiFive

There is a famous quote, misattributed to Gandhi, "first they ignore you, then they laugh at you, then they fight you, then you win." Nobody is laughing at RISC-V any more. The "modest goal" of RISC-V to "become the industry standard for all computing device" is by no means inevitable, but it is also not impossible.

Background

Full details of the upcoming evening, including a link for registration, are on the ESD Alliance website.

If you want some background reading or RISC-V, then take a look my posts:

There is also a lot of material from the RISC-V fifth workshop, including the presentation slides and videos, on the RISC-V Foundation's website.

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