Litho Physical Analyzer PLUS

Next week it is the SPIE Advanced Lithography Conference (and DVCon, and MWC in Barcelona, busy week). Cadence will be presenting a paper on Litho Physical Analyzer PLUS (LPA PLUS). This is a product suited for 7nm and 5nm. It is a joint development between ASML, imec and Cadence that was announced this morning.

The motivation is that at advanced nodes, the definition of design rules and process options need to be tightly optimized to provide the best tradeoff between manufacturability and PPA (performance, power, area). However, process teams don't have a lot of design knowledge and design teams don't have access to all the process information. One change that has been coming gradually is that it is not possible to capture absolutely everything in a single set of design rules. Some patterns that are known to be "weak", that is, liable to print badly, are compliant with the rules but are still inadvisable. There is already a problem with the size of rule decks, so if the rules were expanded to cover every contingency then either they would become unmanageable or they would have to be simplified, eliminating a lot of good patterns along with the bad ones.

The Tachyon OPC engine used by imec 7/5nm process has been integrated into Cadence Litho Physical Analyzer (LPA) to perform lithography checks using the foundry process recipes, and to leverage LPA integration in both the custom and digital flows, as well as a standalone signoff. Tachyon is actually an ASML product that resulted from its acquisition of Brion Technologies a decade ago.

Most problems go through a life-cycle. They start with a verification tool that identifies problems, maybe a dozen. They are fixed by hand. Next process node, the verification tool identifies problems, but now there are ten thousand. Obviously, they can't be fixed manually, verification needs to be more integrated into the tools. Eventually, whatever produces the problems needs to be updated to be whatever-it-is-aware so it doesn't generate problems. Think of how crosstalk went from something to identify errors to an integral part of physical design. Litho hot spots and LPA PLUS are somewhere in the middle of the lifecycle now.

LPA PLUS can be launched either from Innovus place & route, Virtuoso custom design, or standalone. LPA first processes the design database to identify hierarchy, decomposes the layout for coloring and then applies pattern matching to identify locations requiring simulation. The layout then passes to the Tachyon OPC tool for optical process correction and model-based lithography verification. The hotspots and contours are processed by LPA for generation of hotspot markers and fixing guidelines, and then feeding all this information back into the design environment. The flow was developed and tested on 7nm, but it can be migrated to smaller or larger nodes.

In Virtuoso, the analysis can be launched and the results shown in the annotation browser. However, as is the nature of custom design, fixup is manual.

However, in Innovus, rerouting can be done before re-running the checks. In the example below, the number of hot spots is 671 before fixing, and 2 afterwards (which can be inspected and perhaps fixed manually).

The diagram below shows the flow and how the ASML and Cadence technologies work together. ASML supplies the Tachyon software, Cadence supplies the LPA software. The foundry, imec in the prototype, supplies encrypted recipes and models. Cadence also supplies an encrypted LPA technology file. This results in a flow that can identify the problem areas without revealing secrets of the process.

The paper was presented yesterday 28th Februrary, at the SPIE Advanced Lithography Conference. It is paper 10147-4: In-design and signoff lithography physical analysis for 7nm/5nm by Cyrus Tabery, Yi Zou, Vincent Arnoux, Praveen Raghavan, Ryoung-han Kim, Michel Côté, Luca Matti, Ya-Chieh Lai and Philippe Hurat.