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Cadence was created from the merger of SDA and ECAD, as you probably know. SDA had a number of products, by then including a layout editor that would become Virtuoso, which included an interactive DRC that would become Diva in the era when most Cadence products (including the Cadence name itself) had some connection to music. ECAD had two main products: a design rule checker (DRC) called Dracula, and a symbolic layout product called Symbad. So from day one, Cadence had two DRC products.
Dracula would become the industry standard, the tool that every single semiconductor design in the world was checked with before tapeout. Since the story of why Calibre came to hold that position doesn't reflect well on Cadence, I'm a bit reluctant to tell it, but it is 20 years in the past. Even though I inherited the Cadence physical verification business for a time about 15 years ago, by then I was just managing its decline. Physical verification just happened to be part of the custom IC (CIC) division, but my big focus was to improve Virtuoso, where we'd taken our collective eyes off the ball and were underinvesting. Silicon Canvas's Laker was making some inroads especially in Asia, and we were not going to lose our Virtuoso franchise, especially on my watch. We didn't.
When I joined VLSI Technology in the early 80s, one of my first jobs was to work on the DRC and also create VLSI's circuit extractor. Although they do very different things, the key underlying technology is similar: processing polygons that have sizes, and spacings, and overlaps. While the DRC checks that all the dimensions are within tolerance, the extractor is more concerned with overlaps. Where poly crossed diffusion, you had a transistor. Where certain triplets of layers (such as metal1, contact, and diffusion) overlapped, you had an electrical connection. We didn't worry about either resistance or sidewall capacitance—both were insignificant compared to bulk and gate capacitance—and we were still in the happy days of Dennard scaling, where most of the capacitance was gate capacitance, so each process generation was smaller and faster for the same power.
When I first heard about circuit extraction—a program that derives the transistor netlist from just the layout—it seemed impossible. There are polygons all over the place on all sorts of layers. The method to bring order to the chaos was to focus just on the edges of the polygons. They were then sorted from the bottom of the chip to the top. With everything ordered like that, it was possible to run a scanline across the chip so that only edges near the scanline needed to be considered. For extraction, it was only necessary to consider edges that actually crossed the scanline since there were no effects that required considering polygons that didn't overlap completely. For DRC, a strip of edges needed to be considered since a spacing or width error could occur parallel to the scanline, and thus involve two edges that never touched the scanline simultaneously. Edges were not the most compact representation, and a later improvement was to fracture into trapezoids and optimize the handling of rectangles, which were almost all the polygons in practice.
Gradually design rules became more complex and the electrical effects that needed to be modeled also got more complex. Dracula became the dominant DRC, used by every semiconductor manufacturer for signoff. But it was flat; that is, the first thing it did was instantiate all the repeated elements such as memory bit cells and standard cells. Then it would analyze the entire design. But there is a big problem doing this. Once you've checked that a bitcell is DRC-clean once, there is no need to check it again—let alone several thousand times—except perhaps at the very edge of the array where it might interact with neighboring cells. In the simplest of cases, like memories, designers would improve performance by telling the DRC to ignore most of the bitcell array. But that approach wouldn't work for standard cells since the contents of the cell (transistors and low levels of metal) would be the same in each cell, but the routing over the top differed from instantiation to instantiation. The layout wasn't fully hierarchical and a naïve approach would not be good enough.
What was needed was a hierarchical DRC that optimized checking by avoiding most of the redundant checks, not just in the easy memory case, but also in the standard cell case, where some checks could be avoided (anything to do with transistors) and others could not (anything to do with upper levels of metal). Cadence created such a DRC called Vampire (Dracula...Vampire...). However, Cadence made a big misjudgment and Vampire would not read Dracula rule decks. One story I heard is that this was a deliberate decision: they didn't want to cannibalize Dracula sales; they wanted to keep them and sell everyone some copies of Vampire for the large designs. Or that the engineering team for Vampire had assumed everyone had a copy of Dracula too, and reading Dracula decks just wasn't a priority.
Meanwhile, up in Oregon, Mentor was developing a DRC. When I interviewed at Mentor in the mid-90s, Greg Hinckley (who I had worked for at VLSI) told me that he had no idea how the project survived. Every year—for the best part of a decade—they almost canceled the project, since it seemed to be going nowhere and Dracula was dominant. One thing Mentor realized was that if they were going to sell their product, then it had to read Dracula rule decks. Otherwise, they would never even be able to do an evaluation. The product, which of course was Calibre, would run any Dracula deck. That meant that they could perform customer evaluations: run the existing rule decks and show that the answers were the same as Dracula, then spend a bit of time turning on a lot of the hierarchy to show that the answers were the same and it ran a lot faster.
At 0.35um (or 350nm as we would call it today) designs got so large that flat DRCs ran out of steam. The adoption cost of Calibre was low. They could start from the existing rule decks and then incrementally improve them. Vampire was too high, since completely new rule decks would need to be created by hand. Suddenly, it didn't matter that Dracula was the signoff DRC for every semiconductor manufacturer, it couldn't process the designs in an acceptable time, and Calibre was the natural transition for adding hierarchy, not Vampire. I remember asking Lambert van den Hoven of Philips, then Cadence's biggest customer, why they switched and he said it was simply that Calibre could run all the thousands of existing decks. It wouldn't be the optimal way to use the product, but it worked, and if the design was large or they needed to work on it intensively, they could invest in adding hierarchical features to speed it up. This was also a lesson Calibre learned, and their rule decks are not readable by other products.
Another issue was that Cadence (and other EDA companies then) sold software on permanent licenses plus maintenance, so there was no catastrophic fall-off in revenue for DRC, since most customers kept most licenses on maintenance for the bulk of their designs, which were not 0.35um. Cadence lost its dominant position in DRC without any red flags being raised. When I ran custom IC in about 2001, which included physical verification in those days, the numbers still looked reasonably good—even though, by then, we knew that Calibre was the signoff DRC for 0.35um and below and while we remained strong on all the legacy nodes, each new process node resulted in a further erosion of market share.
Design rules got way, way more complicated, and everyone who had a DRC had to make what Clayton Christiansen (in The Innovator's Dilemma) calls "sustaining innovations to keep current". But big changes require some sort of transition, like the change from steel blast furnaces to mini-mills in Clayton's book, or the change from flat to hierarchical DRC. I think the next transition will be the move to massively parallel operation on large server farms of relatively simple servers.
DRCs have been parallel for some time. It is actually easier to parallelize than other areas like simulation. The chip can be split up into tiles and each checked separately in parallel. Of course care needs to be taken at the edges of the tiles. But typically this requires very large servers and relatively small numbers of parallel cores, dozens not hundreds. There is simply a limit to how much things can be parallelized in this way, since the rule decks have got hugely complicated and every rule needs to be checked against every tile. Some separation of rules is possible—for example, coloring rules don't have much to do with other rules—and offers another potential level of parallelization.
The various Cadence DRCs were merged into a single tool with both interactive and batch capabilities, renamed Assura, and became part of PVS, the Physical Verification System, which brings us up to today.
I was looking for some graphics from that pre-internet era, there were some neat looking Dracula ads, but I didn't have any success. But I did find one of the videos that Cadence was famous for back in that era. Back when Cadence was a young upstart, it was smaller than Mentor. At DAC each year, for several years, it would make a video with loud rock music. This one, Amadeus, dates from 1989 when Cadence was two years old and about to overtake Mentor in revenue. As in the 1984 film of the same name, "sometimes a mentor is surpassed." It was the talk of DAC and won some awards. Somehow I don't see Cadence making a video like this today. Enjoy.
Here's another video from that era, CAD to the Bone, from Computervision. For some reason I forget, they were banned from playing this during the show—so instead, the moment the show closed they would crank this out on full volume, once bagpipes finished. In those days, DAC management was very snooty about anything that they thought unsuitable for what they still considered primarily an academic conference. For example, at Compass, we brought a V8 car to the show to showcase our V8 release—but were ordered to take it off the booth by show management. Eventually, the EDA industry told DAC that they would take their trade show somewhere else if they didn't lighten up. Since the revenue from the trade show supported the rest of the conference, they relented.
If you want to skip the long introduction, start at 3:53 (the Cadence blog platform ignores the start information from YouTube or I'd do it for you). If you don't recognize it, it's a parody of George Thorogood and the Destroyers' Bad to the Bone. Crank up the volume and annoy the people in the cubicles around you.
There is a new Silicon Signoff blog starting. The first post is also about physical verification.