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I went to the annual SOI Silicon Valley Symposium recently. As last year, they had to close registration because the room was full. To see what I wrote last year, see FD-SOI: Is It Really a Thing? and like last year, that was the big question. It is like going to a presentation on EUV lithography. There is lots of interesting discussion on facets of technology, but what everyone wants to know is whether anyone is betting their company, or at least some major project, on the technology.
First, read the details, and then I'll give my perspective at the end.
Geoff Lees of NXP (soon to be part of Qualcomm, presumably) led off the day with some presentations about their microcontrollers. At Embedded World, supposedly NXP said that they were broadly migrating their microcontroller family from planar CMOS (at older nodes like 45nm) to 28nm FD-SOI with Samsung as the foundry.
Geoff didn't go that far but he did show five microcontrollers ranging from the low end to the high end all in FD-SOI. He said their main reason for using the process was lower power, that there are microcontrollers that dissipate 1-2W that used to be at 5-8W. These were all based on various flavors of ARM architecture. He had some samples of one of the i.MX chips (as they are called) and said one of the family has been sampling for six months. When asked about non-volatile memory, he said that they depend on the foundry partners for the fundamental bit cell. He said that "MRAM is in its early phases and not yet ready to be a replacement for flash, and I wish RRAM was making more progress." Putting that all together, my guess is Samsung has some roadmap they haven't yet announced and NXP isn't allowed to say anything. Samsung have a foundry day in mid-May so perhaps I'll learn more in a month.
Next was Alain Mutricy of GF. Like Samsung, they licensed the original 28nm FD-SOI technology from ST but decided not to release anything at that node. Instead, they have developed their own 22nm version called 22FDX. This will be manufactured in Fab 1 (in Dresden, Germany). GF also has a FinFET process roadmap, with 14nm licensed from Samsung, skipping 10nm, and developing their own 7nm process, presumably involving a lot of the experts that they acquired with IBM's semiconductor division. They have also committed to building a new 300mm fab in China for 22FDX in a JV with Chengdu Municipality. This new fab is expected to produce older technologies (180/130nm) in 2H of 2018 with 22FDX in 2H of 2019. GF didn't mention the capacity (but later in the day Handel Jones said it was 65K wpm).
GF have also said that they will manufacture the next node on the FD-SOI roadmap, 12FDX, in Dresden and have committed to expand overall capacity there by 50%.
Alain said that 22FDX yield was the same as 28nm (their older planar process). They have "over 70 active engagements" but he wouldn't say how many were taped out and whether any were in volume production. "I want to make a big announcement when it happens, don't try and steal my thunder" he replied.
The weirdest presentation of the day award went to Ron Moore of ARM. I've seen a presentation before (at ARM TechCon?) by his boss Will Abbey about a skunk-works project he initiated to see where FD-SOI fell on the performance curves with different numbers of tracks. Ron showed a little of that. At the end, Ron said that now that GF and Samsung have stepped up to provide manufacturing options, IP providers need to support them, EDA suppliers need to simplify and educate on implementation methodologies, and SOI Consortium members need to organize to build an IoT reference design. That seemed maybe the buildup to some big announcement...but then Ron said that the physical design group of ARM has no FD-SOI libraries available (of course, ARM microprocessors are synthesizable so will work in any process including FD-SOI).
Handel Jones of IBS presented next. He has presented at most of these symposia, including the ones in Europe and Asia. In the early days of FD-SOI he did a lot of analysis of ST's 28nm FD-SOI process from a cost of design and a cost of manufacture point of view, and it looked good. But that was the answer ST wanted, of course, so just how independent the analysis is, is always a little suspect under circumstances like that. Most of what Handel presented was not specific to FD-SOI, growth of the semiconductor industry, growth of IoT ("we have big numbers, everyone has big numbers, but nobody can count though"), 5G being disruptive.
One sweet spot that Handel pointed out that I'd never thought of is the image sensor processor (ISP) that goes with every image sensor. For several years, the standard way to manufacture these is to build the image sensor, then thin the wafer so that the light can come in through what was the back of the wafer during manufacturing. The image sensor is then flipped over and attached to the ISP. So it is 3D packaging but without any TSVs. The ISP has to be the same size as the sensor so there is no pressure to go to 16/14nm. However, the image sensor is very sensitive to heat, so FD-SOI with its capability to go to really low voltage could have a niche here. There are one or two cameras in every one of the billion+ cell phones shipped each year, so it is a big market.
Handel speculated on why FD-SOI has not "happened" yet. Is it "like EUV, always a few years out"? It has only 40-ish masks so should be cost effective but it also needs capacity. GF committed capacity before there was demand to solve that problem. There needs to be IP since nobody can design a chip entirely on their own these days, at the very least they need standard interfaces, and microprocessors. NXP earlier talked about some real production chips that are close to being in the market. So there has been a lot of progress.
Handel thinks that in a couple of years there will be 22nm FD-SOI capacity of 135,000 wpm, which is less, but in the ballpark of 28nm foundry capacity.
The day finished with a panel session on design technology ecosystem readiness, moderated by Adele Hars. The panelists were Wayne Dai of Verisilicon, Sam George of GF, John Koeter of Synopsys, Jayanta Lahiri of Invecas, Christophe Maleville of Soitec, Ron Moore of ARM and Samir Patel of Sankalp Semiconductor.
Adele came out gunning for Ron by asking what ARM's role is in the FD-SOI ecosystem. Ron said ARM was an early participant in SOI technology through a long-term relationship with IBM, but when FinFETs came in they disappeared a little. They currently see an invigoration of the ecosystem.
Next she tossed a soft-ball to Sam of GF about expanding capacity in Germany and a new fab in China. He said that it means demand for FDX and FD-SOI in general is very high. It is at once both an advanced node but solidly in the mainstream. The customer base is not the bleeding-edge guys who do everything themselves, but the next wave of more risk-averse customers who want a whole portfolio.
Jayanta was asked about holes in the ecosystem. He admitted he's only been in the job a couple of months but can always see that library selection is a problem for the end user. People are also a little resistant to get into bias and need the EDA ecosystem to make using it easier.
Christophe of Soitec got asked, surprise, about whether the wafer blank suppliers will be ready. His short answer was yes. His longer answer is that they have been working with IBM and others for years. Now they can plan the capacity increase and follow the ramps in various markets. As long as they can plan, they will do it.
John said that they have designed IP for multiple FD-SOI processes but Samsung is the only one that is public. There is more in flight but he can't disclose anything.
Samir has ported lots of IP to FD-SOI from bulk. The biggest issue has been stability of the foundries but now both GF and Samsung are there with capacity and IP is available that can change. But there are still some gaps.
Next the panel discussed the general state of the design ecosystem and its readiness. Sam pointed out that Samsung has design in the market place, NXP has designs taped out, Dream Chip has designs that are done, including network-on-chip, LPDDR4, USB, and so on. Targeted customer engagements will drive standardization and get the IP portfolio to 100% as designs pick up. Bias is a big potential positive, since some blocks have achieved over 50% power reduction. But you have to think of it like DVFS, it is more involved but the flows and IP support it.
Wayne emphasized the need for some killer application. People don’t like change. Heat in camera is a big deal so that could be the highest volume in FD-SOI short term, as I discussed above.
Jayanta pointed out that another advantage of FD-SOI is that at low voltage, variability is huge. But you can use the bias to trim and not be completely stuck in the worst-case corner. Samir and John admitted that for digital planar everything had been made so simple that designers don't need to understand the transistors so well. The digital guys, but not the analog guys, have forgotten about bias.
Sam was asked whether GF would second-source 22FDX and said it was differentiating technology not available from other competitors.
Ron was put on the spot again for talking about "stepping up" but not having libraries, and whether the POP (processor optimization package) kits would be available. He said they are stepping up and will help optimize cores even if not with ARM physical libraries. They already have experience with A53 and will with M33 this quarter.
Soitec said thinning down to 5nm is not a problem, with no defectivity. The roadmap is to work on the box, currently 15nm. At 22nm, there is a 20nm box so there is some room for following nodes.
Some audience questions, such as whether you should bias individual transistors, went to demonstrate the point that it is not well understood. This was used by a couple of people in the audience as an advertisment for the FD-SOI design tutorials taking place the following day (where I suspect they were going to be among the presenters).
The final question was about Dan Hutcheson's remark at last year's event that FD-SOI was not really dispruptive on its own, but it is an enabler of disruption. Is it? Wayne agreed it was evolutionary. John pointed out that there are, of course, competing technologies but they can't go to such low voltage easily, so low-power edge devices is the sweet spot. Ron got the last word by pointing out that lots of technology seemed disruptive, HiK metal gate? FinFET? Not really that disruptive...except they enabled the smartphone industry. FD-SOI will enable something disruptive.
FD-SOI has historically had all sorts of questions. First, it was just ST, which wasn't enough. Then it was ST and Samsung, but only at 28nm, not enough of a roadmap. Then GF joined in with 22FDX. They added a roadmap to 12FDX. They announced the JV in China to give a 22FDX second source. There remained some questions about IP availability, but people are getting real designs done. The basic IP is all there and more is being added. Companies like NXP have production silicon, and others like Dream Chip and Greenwaves have pre-production designs. If you want to build a chip in FD-SOI and get it manufactured, you can clearly do that. If you are a big company requiring high volume and, perhaps, multiple fabs, you can (or soon will be able to) do that.
The movie Field of Dreams is famous for the phrase "if you build it, they will come." The FD-SOI ecosystem has largely built it. The question still remains for me, will they come?
By "will they come", I mean will significant semiconductor companies commit products that run in high volume to FD-SOI. As someone during the day said, "it's really hard to not follow the Intel roadmap but now there is a choice." I'm not sure the other manufacturers would agree they were following the Intel roadmap, but I have heard anecdotes that nobody was initially interested in FinFET processes. Then Intel announced TriGate (FinFET) and then nobody wanted to hear about anything else.
Field of Dreams had a happy ending. Let's see if FD-SOI does.