Virtuoso System Design Platform

Cadence was already talking about chip-package-board back in 2000 when I was putting together presentations during my last tour of duty. Around then, it started to become impossible to design the chip, especially the power network, to be robust without also taking account of parasitics in the package and on the board. But since then, the world has grown a lot more complex. Clock speeds have increased, of course, but we have also moved into the era of heterogeneous integration with integration of multiple die inside the package, and a variety of packaging technologies used to do this.

The pictures below give some examples:

• Integration of gallium-arsenide, gallium-nitride, and CMOS die in a single package
• Similar integration on an interposer (often called 2.5D)
• Integrated fan-out approach giving interposerless integration
• Stacking 28nm die, along with a 45nm die (probably analog or RF) and a bleeding-edge 10nm digital die in the same package

Only the highest volume products can be built in a leading-edge node, most notably chips for cellphones, which ship in incredible volumes. But even they often have memory in the same package, either wire-bonded or using the 3D packaging technologies that have moved into high-volume manufacturing in the last year or two.

The Traditional Model

The traditional way to design has been "over the wall". The chip is designed largely independently of the package, usually with estimated parasitics for loading the I/Os. The package is designed in its own environment. The package is placed on the board in the PCB design system. Increasingly there has been limited connection between the three domains, especially in the highest speed designs. But the complexity of modern designs, and the schedule pressure, mean that what is required is a direct connection. The chip designer can open up the chip in the context of the environment in which it will operate, not just the package itself but aspects of the other die in a multi-die design.

Systems also often require components that are built in different processes. RF, and even high-performance analog, are attractive to build in the best choice of semiconductor process, and then put the system together inside a complex package, as in the earlier pictures. This has led to an environment with more complex packaging options, and a requirement to be able to create these and analyze the signal integrity. Together, these approaches are known as "More than Moore" since creating a system is no longer simply about driving to the next node using scaling.

Introducing Virtuoso System Design Platform

Cadence has two main world-class technologies in this area. First, the Virtuoso platform for custom IC design; second, Allegro/Sigrity systems for package/PCB design and analysis. Today we announced the Virtuoso System Design Platform which unifies these technologies. This creates a vertically integrated flow from IC through package and onto the PCB. The chip can be designed in the context of the system, with real-world data rather than estimated parasitics. There is a single hierarchical schematic for the whole system, which immediately leads to seamless LVC checking of ICs in the context of the final system, and to system-aware electrical signoff. The diagram below shows how all the various pieces tie together.

This integration enables two flows:

• A top-down implementation flow, for actually creating these complex integrations of chips, package, and board
• A bottom-up analysis flow that feeds board and package information up so that the IC can be designed in a system-aware environment

Of course this holistic approach can be used for the creation and analysis of single-chip designs, but the focus is on the more complex systems with multiple die in heterogeneous processes. The engineering team can design concurrently across the chip, package, and board, with everyone having the most up-to-date data, saving time and minimizing errors.