Get email delivery of the Cadence blog featured here
"It takes a village to raise a child," as the African proverb says. It seems to take a good part of the semiconductor ecosystem to design a 7nm CCIX test vehicle.
CCIX is quite new so here's a little review. It stands for Cache Coherent Interconnect for Accelerators. Yes, I know "accelerators" starts with "A", but then you wouldn't be able to call it "see-six, which is the way it is pronounced. As I've written several times before (see Are General Purpose Microprocessors Over? for a recent take), the power envelope means that processor clock rates cannot go up. And architects don't have any new tricks up their sleeves to wring performance at a fixed clock rate. So that leaves specialized processors as the only way to go. Some of these are custom designs like the Google TPU that they put on all new servers, or Intel's own Myriad X. Some are GPUs, especially NVIDIA. Intel is using FPGAs from their programmable solutions group (that Altera has become). CCIX was announced by everyone who wasn't Intel (or NVIDIA), namely Arm, AMD, Qualcomm, Huawei, Xilinx, and Mellanox, so that systems involving something other than Intel processors and FPGAs could build products that interoperated. Obviously servers from Arm, if they become successful, will need accelerators, too, and probably not Altera/Intel FPGAs. The consortium is open though, and anyone can join.
The huge development in deep learning, especially in the training phase, is not that well suited to general-purpose processors, so this is another driver that makes CCIX so timely. But security, search, 5G network protocol offload, and more will all leverage the high-performance fabric to link specialized processors with the main server processors.
As system architectures have become more complex, any particular item of data may be in a number of places (like cache memories). Or even in more than one. With simpler architectures, coherence was usually implemented in software but adding inefficiencies like flushing the cache. That required software to know the system configuration (or allowed just limited types of configuration). In the current environment, where we want to use accelerators in systems where the designers didn't know all the details at the time the accelerators were designed, a hardware-based approach is required. All the main network-on-chip (NoC) vendors such as Arm or Arteris have added coherency in recent years.
CCIX is a high-performance standard, so there is not a lot of point in building implementations in old processes. So to you need a high-performance process. TSMC has 7nm FinFET. You need a processor and its system buses—Arm provides that. You need an offload processor fabric—Xilinx provides that. Most obviously, you need a CCIX implementation and PHY—Cadence provides that (and memory and other interfaces). The test chip will provide silicon proof to show the capabilities of a high-performance server-class Arm processor working through a coherent fabric to a Xilinx accelerator (also manufactured by TSMC like all Xilinx arrays for several years).
The recent announcement is of the collaboration. The test chip is expected to tapeout in Q1 2018 for delivery later in the year.
The announcement crossed the wire today, but there may be more information at TSMC's OIP Ecosystem Forum meeting, which is this coming Wednesday. The agenda for the day can be found on TSMC's website. I will be there and will have at least a couple of reports on what I manage to get written down during the day.
Cadence is presenting several things:
9:55 - 10:05—There is a brief "partner feature talk" by Anirudh Devgan
11:05 - 11:35—In the IP track, Cadence will present High-Performance Memory IP and Subsystem for Automotive Applications
11:35 - 12:05—In the EDA track, Cadence will present Generating DRC and Electrically Correct Placed-and-Routed Arrays Using the TSMC 7nm Process
13:30 - 14:00—In the IP track, Cadence will present High-Speed Interconnect IPs for High-Performance Computing and Enterprise Applications
14:30 - 15:00—Again on the IP track, Cadence and Arm will present Achieving Optimal PPA for Arm Cortex-A75 Processors Using TSMC FinFET Technology with Cadence Digital Tools
15:30 - 16:00—In the Services track, Cadence and Microsemi will present Using Pegasus Verification System for Advanced-Node Design Rule Check (DRC)
16:30 - 17:00—In the EDA track, Cadence will present System Planning for CoWoS and InFO Technologies
Cadence will also have our Expert Bar in the Ecosystem Pavilion.
Sign up for Sunday Brunch, the weekly Breakfast Bytes email.